component
CD4030BPWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownCD4030BPWR
Texas Instruments · Logic Gates · TSSOP-14
CD4030BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of gate 1 (J = A XOR B); inputs are CMOS-protected and limited to -0.5V to VDD+0.5V. |
| 2 | B | input | Input B of gate 1 (J = A XOR B); inputs are limited to -0.5V to VDD+0.5V. |
| 3 | J | output | Output of gate 1, J = A XOR B. |
| 4 | K | output | Output of gate 2, K = C XOR D. |
| 5 | C | input | Input C of gate 2 (K = C XOR D); inputs are limited to -0.5V to VDD+0.5V. |
| 6 | D | input | Input D of gate 2 (K = C XOR D); inputs are limited to -0.5V to VDD+0.5V. |
| 7 | VSS | power_in | Ground / negative supply reference; VDD is specified relative to VSS. |
| 8 | E | input | Input E of gate 3 (L = E XOR F); inputs are limited to -0.5V to VDD+0.5V. |
| 9 | F | input | Input F of gate 3 (L = E XOR F); inputs are limited to -0.5V to VDD+0.5V. |
| 10 | L | output | Output of gate 3, L = E XOR F. |
| 11 | M | output | Output of gate 4, M = G XOR H. |
| 12 | G | input | Input G of gate 4 (M = G XOR H); inputs are limited to -0.5V to VDD+0.5V. |
| 13 | H | input | Input H of gate 4 (M = G XOR H); inputs are limited to -0.5V to VDD+0.5V. |
| 14 | VDD | power_in | Positive supply; recommended 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4030BPWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4030bpwr-etched.step/cd4030bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4030bpwr.step/cd4030bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
04f95a759b6780e5, retrieved 2026-10-07, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).