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EG1168
Public Made by Adomby adom
EG Micro Gate Drivers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownEG1168
EG Micro · Gate Drivers · SOP-16
EG1168 from EG Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF5V | output | 5V reference output that supplies up to 20mA drive current (maximum output current 20mA), and a 1uF ceramic bypass capacitor is recommended close to this pin. |
| 2 | EN | input | Chip enable pin with a 1.2V comparison threshold; below 1.2V the chip enters standby and turns off the 5V output. |
| 3 | SD | input | A high level turns off the HO and LO outputs cycle by cycle for protection, and a low level allows PWM output. |
| 4 | PWMIN | input | Logic input signal that is converted into two symmetrical half-bridge and push-pull PWM outputs, with an internal 200K pull-down that turns both power MOSFETs off when the input is left floating. |
| 5 | VSS | power_in | Chip signal ground (AGND) for the control and op-amp circuitry. |
| 6 | INP | input | Non-inverting input of the internal op-amp, with an input voltage range of -0.3V to 5.3V. |
| 7 | INN | input | Inverting input of the internal op-amp, with an input voltage range of -0.3V to 5.3V. |
| 8 | AMPO | output | Output of the internal op-amp, with an output voltage range of 0V to REF5V. |
| 9 | SDLIN | input | Current comparator input for the low-side MOS transistor, with a 160mV to 200mV threshold relative to COM (180mV typical). |
| 10 | LO | output | Output that drives the gate of the low-side power MOS transistor to control its turn-on and turn-off. |
| 11 | COM | power_in | Chip power ground (PGND) for the output driver stage. |
| 12 | VCC | power_in | Chip supply for the low-side circuitry, with a voltage range of 10V to 20V and undervoltage protection. |
| 13 | SDHIN | input | Current comparator input for the high-side MOS transistor, with a 160mV to 200mV threshold relative to VS (180mV typical). |
| 14 | VS | power_in | High-side floating ground reference for the high-side driver, which can be up to 600V with respect to ground. |
| 15 | VB | power_in | High-side floating supply for the bootstrap high-side driver, with a rating of -0.3V to 600V and undervoltage protection. |
| 16 | HO | output | Output that drives the gate of the high-side power MOS transistor to control its turn-on and turn-off. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | EG Micro |
| Package | SOP-16 |
| Category | Motor Driver ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 自举高端VB电源 (bootstrap high-side VB supply, absolute max) | VB | -0.3 | 600 | V | 10 | ||
| 低端电源 (low-side VCC supply, absolute max) | VCC | -0.3 | 20 | V | 10 | ||
| 低端输出 (LO output, absolute max; upper limit printed as VCC+0.3) | LO | -0.3 | V | 10 | |||
| 低端比较器输入 (low-side comparator input, absolute max) | SDLIN | -0.3 | 5 | V | 10 | ||
| 低压运放端口 (op-amp ports INP, INN, AMPO, absolute max) | INP、INN、AMPO | -0.3 | 5.5 | V | 10 | ||
| 控制端口 (control ports SD, PWMIN, absolute max) | SD、PWMIN | -0.3 | 20 | V | 10 | ||
| 环境温度 (ambient temperature) | TA | -45 | 125 | ℃ | 10 | ||
| 储存温度 (storage temperature) | Tstr | -65 | 150 | ℃ | 10 | ||
| 焊接温度 (soldering temperature) | TL | 300 | ℃ | T=10S | 10 | ||
| 高压电源 VB (high-voltage VB supply range) | VB | 10 | 600 | V | 11 | ||
| VCC 电源 (VCC supply range) | VCC | 10 | 20 | V | 11 | ||
| VCC 静态电流 (VCC quiescent current) | Ivcc | 1 | 1.5 | mA | VCC=12V | 11 | |
| VB 静态电流 (VB quiescent current) | IB | 50 | 150 | uA | VBS=12V | 11 | |
| 输入信号高电位 (logic input high level) | Vin(H) | 2.5 | V | HIN、LIN 输入信号 | 11 | ||
| 输入信号低电位 (logic input low level) | Vin(L) | -0.3 | 0 | 1 | V | HIN、LIN 输入信号 | 11 |
| 输入逻辑高电平电流 (logic input high-level current) | Iin(H) | 20 | uA | Vin=5V | 11 | ||
| 输入逻辑低电平电流 (logic input low-level current) | Iin(L) | -20 | uA | Vin=0V | 11 | ||
| VCC 开启电压 (VCC turn-on voltage) | VCC（ON） | 7.5 | 8.5 | 9.5 | V | VCC 相对 VSS | 11 |
| VCC 关闭电压 (VCC turn-off voltage) | VCC（OFF） | 7 | 7.9 | 8.9 | V | VCC 相对 VSS | 11 |
| VB 开启电压 (VB turn-on voltage) | VB（ON） | 6.2 | 7.2 | 8.1 | V | VB 相对 VS | 11 |
| VB 关闭电压 (VB turn-off voltage) | VB（OFF） | 6 | 6.9 | 7.8 | V | VB 相对 VS | 11 |
| 5V 基准输出 (5V reference output) | REF5V | 4.6 | 4.8 | 5 | V | VCC 开启，VCC=12V | 11 |
| 线性调整率 (line regulation) | ΔVREF | 3 | 50 | mV | VCC=10V to 20V | 11 | |
| 负载调整率 (load regulation) | ΔVREF | 5 | 50 | mV | IL=0 to 20mA | 11 | |
| 最大输出电流 (maximum REF5V output current) | Iomax | 20 | mA | 11 | |||
| EN 使能比较电压 (EN enable comparison voltage) | Ven | 1.15 | 1.2 | 1.25 | V | 11 | |
| 运放输入失调电压 (op-amp input offset voltage) | VAOS | 10 | mV | 11 | |||
| 运放输入电压范围 (op-amp input common-mode range) | VAICR | -0.3 | 5.3 | V | 11 | ||
| 运放输出电压范围 (op-amp output voltage range; upper limit printed as REF5V) | Vout | 0 | V | 11 | |||
| 运放输出电流能力 (op-amp output current capability) | Iamp | 10 | mA | 11 | |||
| 高端电流比较器阈值 (high-side current comparator threshold) | SDHIN | 160 | 180 | 200 | mV | SDHIN 相对 VS 电压 | 12 |
| 低端电流比较器阈值 (low-side current comparator threshold) | SDLIN | 160 | 180 | 200 | mV | SDLIN 相对 COM 电压 | 12 |
| PWMIN到输出 开延时 (PWMIN to output turn-on delay) | Ton | 300 | 400 | nS | 见图 7-1 | 12 | |
| PWMIN到输出 关延时 (PWMIN to output turn-off delay) | Toff | 170 | 200 | nS | 见图 7-1 | 12 | |
| PWMIN到输出 上升时间 (PWMIN to output rise time) | Tr | 120 | 200 | nS | 见图 7-1，CL=10nF | 12 | |
| PWMIN到输出 下降时间 (PWMIN to output fall time) | Tf | 80 | 100 | nS | 见图 7-1，CL=10nF | 12 | |
| SD到输出 开延时 (SD to output turn-on delay) | Ton | 300 | 400 | nS | 见图 7-2 | 12 | |
| SD到输出 关延时 (SD to output turn-off delay) | Toff | 170 | 400 | nS | 见图 7-2 | 12 | |
| SD到输出 上升时间 (SD to output rise time) | Tr | 120 | 200 | nS | 见图 7-2，CL=10nF | 12 | |
| SD到输出 下降时间 (SD to output fall time) | Tf | 100 | 100 | nS | 见图 7-2，CL=10nF | 12 | |
| PWMIN 最小低电平时间 (PWMIN minimum low-level time) | TLmin | 100 | nS | 见图 7-3 | 12 | ||
| LO、HO 输出拉电流 (LO/HO source current, pulsed) | IO+ | 1.8 | 2 | A | Vo=0V,VIN=VIH PW≤10uS | 12 | |
| LO、HO 输出灌电流 (LO/HO sink current, pulsed) | IO- | 2 | 2.5 | A | Vo=12V,VIN=VIL PW≤10uS | 12 |
CAD (KiCad official)
- Symbol:
EG1168 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
eg1168-etched.step/eg1168-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);eg1168.step/eg1168.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: EG Micro datasheet (16 pp, sha256
4dfb7cc2fb7f50a3, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).