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TPS74801QRGWRQ1

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Texas Instruments Linear Voltage Regulators (LDO), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS74801QRGWRQ1

Texas Instruments · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)

TPS74801QRGWRQ1 from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage; needs a ceramic capacitor of total typical capacitance ≥ 2.2 μF to ground for stability.
2 NC unconnected No connection; can be left floating or connected to GND for better thermal contact to the top-side plane.
3 NC unconnected No connection; can be left floating or connected to GND for better thermal contact to the top-side plane.
4 NC unconnected No connection; can be left floating or connected to GND for better thermal contact to the top-side plane.
5 IN power_in Input to the device.
6 IN power_in Input to the device.
7 IN power_in Input to the device.
8 IN power_in Input to the device.
9 PG output Open-drain, active-high power-good output that goes high-impedance when VOUT exceeds the PG trip threshold; use a 10 kΩ to 1 MΩ pull-up to a supply up to 5.5 V, or leave unconnected if not needed.
10 BIAS power_in Bias input voltage for the error amplifier, reference, and internal control circuits.
11 EN input Enable pin: high enables the regulator, low puts it into shutdown mode; must not be left unconnected.
12 GND power_in Ground.
13 NC unconnected No connection; can be left floating or connected to GND for better thermal contact to the top-side plane.
14 NC unconnected No connection; can be left floating or connected to GND for better thermal contact to the top-side plane.
15 SS passive Soft-start pin: a capacitor to ground sets the start-up time; if left unconnected the soft-start ramp time is typically 200 μs.
16 FB input Feedback connection to the center tap of the external resistor divider that sets the output voltage; must not be left floating.
17 NC unconnected No connection; can be left floating or connected to GND for better thermal contact to the top-side plane.
18 OUT power_out Regulated output voltage; needs a ceramic capacitor of total typical capacitance ≥ 2.2 μF to ground for stability.
19 OUT power_out Regulated output voltage; needs a ceramic capacitor of total typical capacitance ≥ 2.2 μF to ground for stability.
20 OUT power_out Regulated output voltage; needs a ceramic capacitor of total typical capacitance ≥ 2.2 μF to ground for stability.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-20-EP(5x5)
Category Power Management ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 5.5 V min is VOUT + VDO 4
Bias pin voltage range VBIAS 2.7 5.5 V 4
Internal reference (Adj.) VREF 0.796 0.8 0.804 V TA = 25°C 4
Output voltage range VOUT 0.8 3.6 V VIN = 5 V, IOUT = 1.5 A 4
Output voltage accuracy VOUT -2 0.5 2 % 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A 4
Line regulation ΔVOUT/ΔVIN 0.03 %/V VOUT(NOM) + 0.3 ≤ VIN ≤ 5.5 V 4
Load regulation ΔVOUT/ΔIOUT 0.09 %/A 50 mA ≤ IOUT ≤ 1.5 A 4
VIN dropout voltage VDO 60 165 mV IOUT = 1.5 A, VBIAS, VOUT(NOM) ≥ 3.25 V 4
VBIAS dropout voltage VDO 1.31 1.6 V IOUT = 1.5 A, VIN = VBIAS 4
Current limit ICL 2 5.5 A VOUT = 80% × VOUT(NOM) 4
Bias pin current IBIAS 1 2 mA 4
Shutdown supply current ISHDN 1 50 μA VEN ≤ 0.4 V 4
Feedback pin current IFB -1 0.15 1 μA 4
Enable input high level VEN,HI 1.1 5.5 V 4
Enable input low level VEN,LO 0 0.4 V 4
Enable pin current IEN 0.1 1 μA VEN = 5 V 4
PG trip threshold VIT 85 90 94 %VOUT VOUT decreasing 4
PG output low voltage VPG,LO 0.3 V IPG = 1 mA (sinking), VOUT < VIT 4
PG leakage current IPG,LKG 0.1 1 μA VPG = 5.25 V, VOUT > VIT 4
PG trip hysteresis VHYS 3 %VOUT 4
PSRR VIN to VOUT 1 kHz PSRR 60 dB 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 4
PSRR VIN to VOUT 300 kHz PSRR 30 dB 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 4
PSRR VBIAS to VOUT 1 kHz PSRR 50 dB 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 4
PSRR VBIAS to VOUT 300 kHz PSRR 30 dB 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 4
Output noise voltage Vn 25 μVRMS 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 0.001 μF; 25 × VOUT 4
Minimum startup time tSTR 200 μs RLOAD for IOUT = 1 A, CSS = open 4
Soft-start charging current ISS 440 nA VSS = 0.4 V 4
Enable pin hysteresis VEN,HYS 50 mV 4
Enable pin deglitch time VEN,DG 20 μs 4
Thermal shutdown temperature (shutdown) TSD 165 °C Shutdown, temperature increasing 4
Thermal shutdown temperature (reset) TSD 140 °C Reset, temperature decreasing 4
Input voltage range (VIN, VBIAS) VIN, VBIAS -0.3 6 V with respect to GND 2
Enable voltage range VEN -0.3 6 V 2
Power good voltage range VPG -0.3 6 V 2
PG sink current IPG 0 1.5 mA 2
Soft-start voltage range VSS -0.3 6 V 2
Feedback voltage range VFB -0.3 6 V 2
Output voltage range VOUT -0.3 V max is VIN + 0.3 V 2
Operating junction temperature range TJ -40 150 °C 2
Storage junction temperature range TSTG -55 150 °C 2
ESD HBM classification level H2 2000 V Human body model 2
ESD CDM classification level C4B 750 V Charged device model 2
Ambient operating temperature TA -40 125 °C RGW package 2
Junction-to-ambient thermal resistance θJA 35.6 °C/W RGW, 20 pins 3
Junction-to-case (top) thermal resistance θJCtop 33.3 °C/W RGW, 20 pins 3
Junction-to-board thermal resistance θJB 15 °C/W RGW, 20 pins 3
Junction-to-top characterization parameter ψJT 0.4 °C/W RGW, 20 pins 3
Junction-to-board characterization parameter ψJB 15.2 °C/W RGW, 20 pins 3
Junction-to-case (bottom) thermal resistance θJCbot 3.8 °C/W RGW, 20 pins 3

CAD (KiCad official)

  • Symbol: TPS74801QRGWRQ1
  • Footprint: Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm
  • 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps74801qrgwrq1-etched.step / tps74801qrgwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps74801qrgwrq1.step / tps74801qrgwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 70e96182ff0e1fb6, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF