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DSPIC33CK256MC505-E/PT

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Microchip Tech Digital Signal Processors (DSP/DSC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersdspic33ck256mc505-efactory-2.0.0extractor-text

Verified DSPIC33CK256MC505-E/PT

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DSPIC33CK256MC505-E/PT · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 984-page datasheet
  • ✓distributor: lcsc C6183083, digikey 150-DSPIC33CK256MC505-E/PT-ND, mouser 494-33CK256MC505EPT
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-86xukq2n/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.968)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ dspic33ck256mc505-e-pt.kicad_sym✓ dspic33ck256mc505-e-pt.kicad_mod✓ dspic33ck256mc505-e-pt.step
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Contents

README

markdown

DSPIC33CK256MC505-E

Microchip Tech · Digital Signal Processors (DSP/DSC) · TQFP-48(7x7)

DSPIC33CK256MC505-E from Microchip Tech, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RB14 bidirectional Multiplexed pin RP46/PWM1H/RB14: PORTB bit 14 I/O, PPS-remappable RP46 and PWM1H output.
2 RB15 bidirectional Multiplexed pin RP47/PWM1L/RB15: PORTB bit 15 I/O, PPS-remappable RP47 and PWM1L output.
3 RC12 bidirectional Multiplexed pin RP60/RC12: PORTC bit 12 I/O with PPS-remappable RP60.
4 RC13 bidirectional Multiplexed pin RP61/RC13: PORTC bit 13 I/O with PPS-remappable RP61.
5 MCLR input Master Clear input, an active-low Reset to the device that is also used for programming and debugging.
6 RD13 bidirectional Multiplexed pin ANN0/RP77/RD13: analog negative input ANN0, PPS-remappable RP77 and PORTD bit 13 I/O.
7 RC0 bidirectional Multiplexed pin AN12/RP48/RC0: analog input AN12, PPS-remappable RP48 and PORTC bit 0 I/O.
8 RA0 bidirectional Multiplexed pin OA1OUT/AN0/CMP1A/IBIAS0/RA0: op amp 1 output, analog input AN0, comparator 1 channel A input, 50 uA current bias output IBIAS0 and PORTA bit 0 I/O.
9 RA1 bidirectional Multiplexed pin OA1IN-/AN16/RA1: op amp 1 inverting input, analog input AN16 and PORTA bit 1 I/O.
10 RA2 bidirectional Multiplexed pin OA1IN+/AN9/RA2: op amp 1 non-inverting input, analog input AN9 and PORTA bit 2 I/O.
11 RA3 bidirectional Multiplexed pin DACOUT/AN3/CMP1C/RA3: DAC output voltage, analog input AN3, comparator 1 channel C input and PORTA bit 3 I/O.
12 RA4 bidirectional Multiplexed pin OA3OUT/AN4/IBIAS3/RA4: op amp 3 output, analog input AN4, 50 uA current bias output IBIAS3 and PORTA bit 4 I/O.
13 AVDD power_in Positive supply for analog modules; must be connected at all times.
14 AVSS power_in Ground reference for analog modules; must be connected at all times.
15 RC1 bidirectional Multiplexed pin OA3IN-/AN13/CMP1B/ISRC0/RP49/RC1: op amp 3 inverting input, analog input AN13, comparator 1 channel B input, 10 uA current source ISRC0, PPS RP49 and PORTC bit 1 I/O.
16 RC2 bidirectional Multiplexed pin OA3IN+/AN14/CMP2B/ISRC1/RP50/RC2: op amp 3 non-inverting input, analog input AN14, comparator 2 channel B input, 10 uA current source ISRC1, PPS RP50 and PORTC bit 2 I/O.
17 RC6 bidirectional Multiplexed pin AN19/IBIAS1/RP54/RC6: analog input AN19, 50 uA current bias output IBIAS1, PPS RP54 and PORTC bit 6 I/O.
18 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
19 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
20 RC3 bidirectional Multiplexed pin AN15/CMP2A/IBIAS2/RP51/RC3: analog input AN15, comparator 2 channel A input, 50 uA current bias output IBIAS2, PPS RP51 and PORTC bit 3 I/O.
21 RB0 bidirectional Multiplexed pin OSCI/CLKI/AN5/RP32/RB0: oscillator crystal input or external clock input, analog input AN5, PPS RP32 and PORTB bit 0 I/O.
22 RB1 bidirectional Multiplexed pin OSCO/CLKO/AN6/RP33/RB1: oscillator crystal output or CLKO, analog input AN6, PPS RP33 and PORTB bit 1 I/O; it has increased current drive strength and is toggled during programming.
23 RD10 bidirectional Multiplexed pin AN18/ISRC3/RP74/RD10: analog input AN18, 10 uA current source ISRC3, PPS RP74 and PORTD bit 10 I/O.
24 RC7 bidirectional Multiplexed pin AN7/ISRC2/RP55/RC7: analog input AN7, 10 uA current source ISRC2, PPS RP55 and PORTC bit 7 I/O.
25 RB2 bidirectional Multiplexed pin OA2OUT/AN1/CMP1D/CMP2D/RP34/INT0/RB2: op amp 2 output, analog input AN1, comparator 1 and 2 channel D inputs, PPS RP34, external interrupt INT0 and PORTB bit 2 I/O.
26 RB3 bidirectional Multiplexed pin PGD2/OA2IN-/AN8/RP35/RB3: programming/debugging data I/O channel 2, op amp 2 inverting input, analog input AN8, PPS RP35 and PORTB bit 3 I/O.
27 RB4 bidirectional Multiplexed pin PGC2/OA2IN+/AN17/RP36/RB4: programming/debugging clock channel 2, op amp 2 non-inverting input, analog input AN17, PPS RP36 and PORTB bit 4 I/O.
28 RC8 bidirectional Multiplexed pin RP56/ASDA1/SCK2/RC8: PPS RP56, alternate I2C1 data ASDA1, SPI2 clock SCK2 and PORTC bit 8 I/O; it has increased current drive strength.
29 RC9 bidirectional Multiplexed pin RP57/ASCL1/SDI2/RC9: PPS RP57, alternate I2C1 clock ASCL1, SPI2 data in SDI2 and PORTC bit 9 I/O; it has increased current drive strength.
30 RD8 bidirectional Multiplexed pin RP72/SDO2/PCI19/RD8: PPS RP72, SPI2 data out SDO2, PWM input PCI19 and PORTD bit 8 I/O; it has increased current drive strength.
31 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
32 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
33 RB5 bidirectional Multiplexed pin PGD3/RP37/RB5: programming/debugging data I/O channel 3, PPS RP37 and PORTB bit 5 I/O.
34 RB6 bidirectional Multiplexed pin PGC3/RP38/RB6: programming/debugging clock channel 3, PPS RP38 and PORTB bit 6 I/O.
35 RB7 bidirectional Multiplexed pin TDO/AN2/RP39/RB7: JTAG test data output, analog input AN2, PPS RP39 and PORTB bit 7 I/O.
36 RB8 bidirectional Multiplexed pin PGD1/AN10/RP40/SCL1/RB8: programming/debugging data I/O channel 1, analog input AN10, PPS RP40, I2C1 clock SCL1 and PORTB bit 8 I/O.
37 RB9 bidirectional Multiplexed pin PGC1/AN11/RP41/SDA1/RB9: programming/debugging clock channel 1, analog input AN11, PPS RP41, I2C1 data SDA1 and PORTB bit 9 I/O.
38 RC4 bidirectional Multiplexed pin RP52/RC4: PORTC bit 4 I/O with PPS-remappable RP52.
39 RC5 bidirectional Multiplexed pin RP53/RC5: PORTC bit 5 I/O with PPS-remappable RP53.
40 RC10 bidirectional Multiplexed pin RP58/RC10: PORTC bit 10 I/O with PPS-remappable RP58.
41 RC11 bidirectional Multiplexed pin RP59/RC11: PORTC bit 11 I/O with PPS-remappable RP59.
42 VSS power_in Ground reference for logic and I/O pins; must be connected at all times.
43 VDD power_in Positive supply for peripheral logic and I/O pins; must be connected at all times.
44 RD1 bidirectional Multiplexed pin RP65/PWM4H/RD1: PPS RP65, PWM4H output and PORTD bit 1 I/O.
45 RB10 bidirectional Multiplexed pin TMS/RP42/PWM3H/RB10: JTAG test mode select, PPS RP42, PWM3H output and PORTB bit 10 I/O; a pull-up is connected during programming or when JTAG is enabled, limiting the maximum pin voltage to 3.6V, otherwise up to 5.5V if JTAG is disabled.
46 RB11 bidirectional Multiplexed pin TCK/RP43/PWM3L/RB11: JTAG test clock input, PPS RP43, PWM3L output and PORTB bit 11 I/O.
47 RB12 bidirectional Multiplexed pin TDI/RP44/PWM2H/RB12: JTAG test data input, PPS RP44, PWM2H output and PORTB bit 12 I/O.
48 RB13 bidirectional Multiplexed pin RP45/PWM2L/RB13: PPS RP45, PWM2L output and PORTB bit 13 I/O.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -40 125 °C 917
Storage temperature -65 150 °C 917
Voltage on VDD with respect to VSS VDD -0.3 4 V 917
Voltage on any pin that is not 5V tolerant with respect to VSS -0.3 V max printed as VDD + 0.3V 917
Voltage on any 5V tolerant pin with respect to VSS -0.3 5.5 V 917
Maximum current out of VSS pin 300 mA 917
Maximum current into VDD pin 300 mA 917
Maximum current sunk/sourced by any regular I/O pin 15 mA 917
Maximum current sunk/sourced by an I/O pin with increased current drive strength 25 mA pins RB1, RC8, RC9 and RD8 917
Maximum current sunk by a group of I/Os between two VSS pins 75 mA 917
Maximum current sourced by a group of I/Os between two VDD pins 75 mA 917
Maximum current sunk by all I/Os 200 mA 917
Maximum current sourced by all I/Os 200 mA 917
VDD Supply Voltage VDD 3 3.6 V 919
Maximum CPU clock frequency 100 MHz VDD 3.0V to 3.6V 917
Operating temperature range -40 125 °C VDD 3.0V to 3.6V 917
Operating Junction Temperature Range (extended devices) TJ -40 140 °C extended temperature devices 918
Operating Ambient Temperature Range (extended devices) TA -40 125 °C extended temperature devices 918
VDD rise rate to ensure internal power-on reset signal SVDD 0.03 V/ms 0V-3V in 100 ms 919
BOR event on VDD transition high-to-low VBOR 2.68 2.99 V 919
Input High-Level Voltage, I/O pins 5V tolerant and MCLR VIH 5.5 V min printed as 0.8 VDD 925
Input High-Level Voltage, I/O pins 5V tolerant with SDAx, SCLx VIH 2.1 5.5 V SMBus enabled 925
Input High-Level Voltage, I/O pins 5V tolerant with SDAx, SCLx VIH 1.35 V SMBus 3.0 enabled; max printed as VDD 925
Input Low-Level Voltage, I/O pins with SDAx, SCLx VIL 0.8 V SMBus enabled; min printed as VSS 925
Input Current with Pull-up Resistor Enabled ICNPU 175 545 µA VDD = 3.3V, VPIN = VSS 925
Input Current with Pull-Down Resistor Enabled ICNPD 65 360 µA VDD = 3.3V, VPIN = VDD 925
Input Leakage Current, I/O pins and MCLR pin IIL -700 nA VPIN = VSS 925
Input Leakage Current, I/O pins and MCLR pin IIL 700 nA VPIN = VDD 925
Operating Current 10 MIPS IDD 6.7 10 mA -40°C, 3.3V, 10 MIPS (N=1, N2=5, N3=2, M=50, FVCO=400 MHz, FPLLO=40 MHz) 919
Operating Current 10 MIPS IDD 6.5 10 mA +25°C, 3.3V, 10 MIPS (N=1, N2=5, N3=2, M=50, FVCO=400 MHz, FPLLO=40 MHz) 919
Operating Current 10 MIPS IDD 7.2 15 mA +85°C, 3.3V, 10 MIPS (N=1, N2=5, N3=2, M=50, FVCO=400 MHz, FPLLO=40 MHz) 919
Operating Current 10 MIPS IDD 9 22 mA +125°C, 3.3V, 10 MIPS (N=1, N2=5, N3=2, M=50, FVCO=400 MHz, FPLLO=40 MHz) 919
Operating Current 20 MIPS IDD 8.5 12.5 mA -40°C, 3.3V, 20 MIPS (N=1, N2=5, N3=1, M=60, FVCO=480 MHz, FPLLO=280 MHz) 919
Operating Current 20 MIPS IDD 8.3 12.5 mA +25°C, 3.3V, 20 MIPS (N=1, N2=5, N3=1, M=60, FVCO=480 MHz, FPLLO=280 MHz) 919
Operating Current 20 MIPS IDD 8.9 17 mA +85°C, 3.3V, 20 MIPS (N=1, N2=5, N3=1, M=60, FVCO=480 MHz, FPLLO=280 MHz) 919
Operating Current 20 MIPS IDD 10.7 25 mA +125°C, 3.3V, 20 MIPS (N=1, N2=5, N3=1, M=60, FVCO=480 MHz, FPLLO=280 MHz) 919
Operating Current 40 MIPS IDD 12.5 18.5 mA -40°C, 3.3V, 40 MIPS (N=1, N2=3, N3=1, M=60, FVCO=480 MHz, FPLLO=160 MHz) 919
Operating Current 40 MIPS IDD 12.3 18.5 mA +25°C, 3.3V, 40 MIPS (N=1, N2=3, N3=1, M=60, FVCO=480 MHz, FPLLO=160 MHz) 919
Operating Current 40 MIPS IDD 13.1 20 mA +85°C, 3.3V, 40 MIPS (N=1, N2=3, N3=1, M=60, FVCO=480 MHz, FPLLO=160 MHz) 919
Operating Current 40 MIPS IDD 14.5 28 mA +125°C, 3.3V, 40 MIPS (N=1, N2=3, N3=1, M=60, FVCO=480 MHz, FPLLO=160 MHz) 919
Operating Current 70 MIPS IDD 17.8 22 mA -40°C, 3.3V, 70 MIPS (N=1, N2=2, N3=1, M=70, FVCO=560 MHz, FPLLO=280 MHz) 919
Operating Current 70 MIPS IDD 17.7 22 mA +25°C, 3.3V, 70 MIPS (N=1, N2=2, N3=1, M=70, FVCO=560 MHz, FPLLO=280 MHz) 919
Operating Current 70 MIPS IDD 18.3 30 mA +85°C, 3.3V, 70 MIPS (N=1, N2=2, N3=1, M=70, FVCO=560 MHz, FPLLO=280 MHz) 919
Operating Current 70 MIPS IDD 20 35 mA +125°C, 3.3V, 70 MIPS (N=1, N2=2, N3=1, M=70, FVCO=560 MHz, FPLLO=280 MHz) 919
Operating Current 90 MIPS IDD 22.3 28 mA -40°C, 3.3V, 90 MIPS (N=1, N2=2, N3=1, M=90, FVCO=720 MHz, FPLLO=360 MHz) 920
Operating Current 90 MIPS IDD 22 28 mA +25°C, 3.3V, 90 MIPS (N=1, N2=2, N3=1, M=90, FVCO=720 MHz, FPLLO=360 MHz) 920
Operating Current 90 MIPS IDD 23 33 mA +85°C, 3.3V, 90 MIPS (N=1, N2=2, N3=1, M=90, FVCO=720 MHz, FPLLO=360 MHz) 920
Operating Current 90 MIPS IDD 23.5 35 mA +125°C, 3.3V, 90 MIPS (N=1, N2=2, N3=1, M=90, FVCO=720 MHz, FPLLO=360 MHz) 920
Operating Current 100 MIPS IDD 21.8 28 mA -40°C, 3.3V, 100 MIPS (N=1, N2=1, N3=1, M=50, FVCO=400 MHz, FPLLO=400 MHz) 920
Operating Current 100 MIPS IDD 20.7 28 mA +25°C, 3.3V, 100 MIPS (N=1, N2=1, N3=1, M=50, FVCO=400 MHz, FPLLO=400 MHz) 920
Operating Current 100 MIPS IDD 21.4 33 mA +85°C, 3.3V, 100 MIPS (N=1, N2=1, N3=1, M=50, FVCO=400 MHz, FPLLO=400 MHz) 920
Operating Current 100 MIPS IDD 23 38 mA +125°C, 3.3V, 100 MIPS (N=1, N2=1, N3=1, M=50, FVCO=400 MHz, FPLLO=400 MHz) 920
Power-Down Current (Sleep) IPD 0.285 0.7 mA -40°C, 3.3V, VREGS bit (RCON[8]) = 0, LPWREN bit (VREGCON[15]) = 1 922
Power-Down Current (Sleep) IPD 0.32 1 mA +25°C, 3.3V, VREGS bit (RCON[8]) = 0, LPWREN bit (VREGCON[15]) = 1 922
Power-Down Current (Sleep) IPD 1500 5 mA +85°C, 3.3V, VREGS bit (RCON[8]) = 0, LPWREN bit (VREGCON[15]) = 1; typ as printed 922
Power-Down Current (Sleep) IPD 4.5 15 mA +125°C, 3.3V, VREGS bit (RCON[8]) = 1, LPWREN bit (VREGCON[15]) = 0; regulators in High-Power mode 922
Package Thermal Resistance, junction to ambient (48-Pin TQFP 7x7 mm) θJA 62.76 °C/W 48-Pin TQFP 7x7 mm; from package simulation 918

CAD (KiCad official)

  • Symbol: DSPIC33CK256MC505-E
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: dspic33ck256mc505-e-pt-etched.step / dspic33ck256mc505-e-pt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dspic33ck256mc505-e-pt.step / dspic33ck256mc505-e-pt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (984 pp, sha256 49806b12be64e196, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF