component
TLC5615CDGKR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC5615CDGKR
Texas Instruments · Digital To Analog Converters (DACs) · VSSOP-8
TLC5615CDGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Serial data input, read into the 16-bit shift register MSB first while CS is low; logic levels are VIH of at least 2.4 V and VIL of at most 0.8 V at VDD = 5 V. |
| 2 | SCLK | input | Serial clock input whose rising edge shifts data into the input register; it should be held low when CS is high to minimize clock feedthrough, and the maximum rate is about 14 MHz. |
| 3 | CS | input | Active-low chip select; the rising edge of CS transfers the shift register contents to the DAC register, and CS transitions should occur only while SCLK is low. |
| 4 | DOUT | output | Serial data output for daisy-chaining, delayed 16 clock cycles plus one clock width from DIN; it is a totem-pole output that changes on the SCLK falling edge when CS is low and stays at its last bit when CS is high. |
| 5 | AGND | power_in | Analog ground reference for the DAC and output buffer, which should connect to the system analog ground plane with negligible ground drop. |
| 6 | REFIN | input | Buffered high-impedance reference input (about 10 MΩ) whose voltage range is 0 V to VDD-2 V with a nominal 2.048 V, setting the full-scale output to twice the reference voltage. |
| 7 | OUT | output | DAC analog voltage output, rail-to-rail with short-circuit protection, with a range of 0 V to VDD-0.4 V at RL = 10 kΩ and capable of driving a 2 kΩ load. |
| 8 | VDD | power_in | Positive supply, 4.5 V to 5.5 V (5 V nominal), that should be bypassed to AGND with a 0.1 µF ceramic capacitor placed close to the device; absolute maximum is 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TLC5615CDGKR - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
tlc5615cdgkr-etched.step/tlc5615cdgkr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc5615cdgkr.step/tlc5615cdgkr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
48b84c422b1f250c, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).