component
CY23EP09SXI-1HT
Public Made by Adomby adom
Infineon Cypress Semicon Clock Buffers, Drivers, Distributors, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownCY23EP09SXI-1HT
Infineon Cypress Semicon · Clock Buffers, Drivers, Distributors · SOIC-16
CY23EP09SXI-1HT from Infineon Cypress Semicon, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF | input | Reference clock input, 10 MHz to 220 MHz maximum, weak pull-down |
| 2 | CLKA1 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |
| 3 | CLKA2 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |
| 4 | VDD | power_in | Supply voltage, 3.3 V or 2.5 V |
| 5 | GND | power_in | Ground |
| 6 | CLKB1 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |
| 7 | CLKB2 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |
| 8 | S2 | input | Select input bit 2, controls output configuration with S1, weak pull-ups |
| 9 | S1 | input | Select input bit 1, controls output configuration with S2, weak pull-ups |
| 10 | CLKB3 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |
| 11 | CLKB4 | tri_state | Bank B buffered clock output, tri-statable via S2:S1, weak pull-down |
| 12 | GND | power_in | Ground |
| 13 | VDD | power_in | Supply voltage, 3.3 V or 2.5 V |
| 14 | CLKA3 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |
| 15 | CLKA4 | tri_state | Bank A buffered clock output, tri-statable via S2:S1, weak pull-down |
| 16 | CLKOUT | output | Buffered output with internal 5 pF feedback load for PLL; external load adjusts zero delay, weak pull-down |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Cypress Semicon |
| Package | SOIC-16 |
| Category | Clock/Timing |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CY23EP09SXI-1HT - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cy23ep09sxi-1ht-etched.step/cy23ep09sxi-1ht-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy23ep09sxi-1ht.step/cy23ep09sxi-1ht.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Cypress Semicon datasheet (19 pp, sha256
1dc3f01d2ee4c941, retrieved 2026-09-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).