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SN74AC373PWR

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Texas Instruments Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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SN74AC373PWR

Texas Instruments · Latches · TSSOP-20

SN74AC373PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Output Enable input; when low, Q outputs drive the bus; when high, Q outputs are in high-impedance state
2 1Q tri_state 1Q 3-state transparent latch output; follows 1D input when LE is high, latches when LE is low, high-impedance when OE is high
3 1D input 1D data input
4 2D input 2D data input
5 2Q tri_state 2Q 3-state transparent latch output; follows 2D input when LE is high, latches when LE is low, high-impedance when OE is high
6 3Q tri_state 3Q 3-state transparent latch output; follows 3D input when LE is high, latches when LE is low, high-impedance when OE is high
7 3D input 3D data input
8 4D input 4D data input
9 4Q tri_state 4Q 3-state transparent latch output; follows 4D input when LE is high, latches when LE is low, high-impedance when OE is high
10 GND power_in Ground reference pin at 0V potential
11 LE input Latch Enable input; when high, Q outputs follow D inputs (transparent mode); when low, Q outputs hold previous values (latched mode)
12 5Q tri_state 5Q 3-state transparent latch output; follows 5D input when LE is high, latches when LE is low, high-impedance when OE is high
13 5D input 5D data input
14 6D input 6D data input
15 6Q tri_state 6Q 3-state transparent latch output; follows 6D input when LE is high, latches when LE is low, high-impedance when OE is high
16 7Q tri_state 7Q 3-state transparent latch output; follows 7D input when LE is high, latches when LE is low, high-impedance when OE is high
17 7D input 7D data input
18 8D input 8D data input
19 8Q tri_state 8Q 3-state transparent latch output; follows 8D input when LE is high, latches when LE is low, high-impedance when OE is high
20 VCC power_in Power Supply pin; 2V to 6V per recommended operating conditions

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic ICs
Pins 20

CAD (KiCad official)

  • Symbol: SN74AC373PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74ac373pwr-etched.step / sn74ac373pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ac373pwr.step / sn74ac373pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 69fd55b9d0d33ea1, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF