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ADS5281IRGCR

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Texas Instruments Analog To Digital Converters (ADCs), VQFN-64-EP(9x9). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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ADS5281IRGCR

Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-64-EP(9x9)

ADS5281IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1P input Positive differential analog input for channel 1; drive with IN1N around 1.5V common-mode with 2VPP total differential swing maximum.
2 IN1N input Negative differential analog input for channel 1; pair with IN1P around 1.5V common-mode with 2VPP maximum differential swing.
3 AVSS power_in Analog power supply ground.
4 IN2P input Positive differential analog input for channel 2; drive with IN2N around 1.5V common-mode with 2VPP total differential swing maximum.
5 IN2N input Negative differential analog input for channel 2; pair with IN2P around 1.5V common-mode with 2VPP maximum differential swing.
6 AVSS power_in Analog power supply ground.
7 IN3P input Positive differential analog input for channel 3; drive with IN3N around 1.5V common-mode with 2VPP total differential swing maximum.
8 IN3N input Negative differential analog input for channel 3; pair with IN3P around 1.5V common-mode with 2VPP maximum differential swing.
9 AVSS power_in Analog power supply ground.
10 IN4P input Positive differential analog input for channel 4; drive with IN4N around 1.5V common-mode with 2VPP total differential swing maximum.
11 IN4N input Negative differential analog input for channel 4; pair with IN4P around 1.5V common-mode with 2VPP maximum differential swing.
12 LVSS power_in Digital power supply ground.
13 PD input Power-down control input, active high; pull high to enter power-down mode as configured via register 0x0F.
14 LVSS power_in Digital power supply ground.
15 OUT1P output LVDS positive output for channel 1; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
16 OUT1N output LVDS negative output for channel 1; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
17 OUT2P output LVDS positive output for channel 2; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
18 OUT2N output LVDS negative output for channel 2; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
19 OUT3P output LVDS positive output for channel 3; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
20 OUT3N output LVDS negative output for channel 3; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
21 OUT4P output LVDS positive output for channel 4; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
22 OUT4N output LVDS negative output for channel 4; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
23 ADCLKP output LVDS positive frame clock output at 1× sample rate; synchronized with serialized data output.
24 ADCLKN output LVDS negative frame clock output at 1× sample rate; synchronized with serialized data output.
25 LCLKP output LVDS positive bit clock output at 6× sample rate; strobe for capturing 12-bit serialized data words.
26 LCLKN output LVDS negative bit clock output at 6× sample rate; strobe for capturing 12-bit serialized data words.
27 OUT5P output LVDS positive output for channel 5; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
28 OUT5N output LVDS negative output for channel 5; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
29 OUT6P output LVDS positive output for channel 6; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
30 OUT6N output LVDS negative output for channel 6; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
31 OUT7P output LVDS positive output for channel 7; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
32 OUT7N output LVDS negative output for channel 7; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
33 OUT8P output LVDS positive output for channel 8; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
34 OUT8N output LVDS negative output for channel 8; 12-bit serialized ADC data at 1× sample rate with 1200mV common-mode and 350mV differential swing.
35 LVDD power_in Digital and I/O power supply, nominal 1.8V; requires bulk and bypass capacitors to LVSS.
36 LVSS power_in Digital power supply ground.
37 AVSS power_in Analog power supply ground.
38 IN5P input Positive differential analog input for channel 5; drive with IN5N around 1.5V common-mode with 2VPP total differential swing maximum.
39 IN5N input Negative differential analog input for channel 5; pair with IN5P around 1.5V common-mode with 2VPP maximum differential swing.
40 AVSS power_in Analog power supply ground.
41 IN6P input Positive differential analog input for channel 6; drive with IN6N around 1.5V common-mode with 2VPP total differential swing maximum.
42 IN6N input Negative differential analog input for channel 6; pair with IN6P around 1.5V common-mode with 2VPP maximum differential swing.
43 AVSS power_in Analog power supply ground.
44 IN7P input Positive differential analog input for channel 7; drive with IN7N around 1.5V common-mode with 2VPP total differential swing maximum.
45 IN7N input Negative differential analog input for channel 7; pair with IN7P around 1.5V common-mode with 2VPP maximum differential swing.
46 AVSS power_in Analog power supply ground.
47 IN8P input Positive differential analog input for channel 8; drive with IN8N around 1.5V common-mode with 2VPP total differential swing maximum.
48 IN8N input Negative differential analog input for channel 8; pair with IN8P around 1.5V common-mode with 2VPP maximum differential swing.
49 AVDD power_in Analog power supply, nominal 3.3V; requires bulk and bypass capacitors to AVSS.
50 AVDD power_in Analog power supply, nominal 3.3V; requires bulk and bypass capacitors to AVSS.
51 ISET passive External resistor to ground, nominal 56.2kΩ; sets internal bias current to 20μA for ADC operation.
52 TP unconnected Test pin; do not connect or connect to ground.
53 VCM output Common-mode output pin, nominal 1.5V; internally generated reference voltage for input biasing.
54 REFB bidirectional Negative reference voltage input/output; 0.5V nominal internal or external 0.4-0.6V depending on INT/EXT configuration.
55 REFT bidirectional Positive reference voltage input/output; 2.5V nominal internal or external 2.4-2.6V depending on INT/EXT configuration.
56 INT/EXT input Internal/external reference mode select; pull low for external reference mode, high for internal reference mode (default).
57 AVDD power_in Analog power supply, nominal 3.3V; requires bulk and bypass capacitors to AVSS.
58 CLKP input Positive differential ADC sample clock input; operate 10-65MSPS with 0.6-2.2V CMOS or ac-coupled differential signal.
59 CLKN input Negative differential ADC sample clock input; tie to 0V for single-ended clock or drive differentially with CLKP.
60 AVDD power_in Analog power supply, nominal 3.3V; requires bulk and bypass capacitors to AVSS.
61 CS input Serial interface chip select, active low; hold low for at least 24 SCLK periods to execute register write.
62 SDATA input Serial data input; 24-bit word format (8-bit address + 16-bit data), latched on SCLK rising edges when CS is low.
63 SCLK input Serial clock input; up to 20MHz frequency, latches SDATA on rising edges.
64 RESET input Active low asynchronous reset input; pulse low for minimum 100ns to initialize all registers to default values.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-64-EP(9x9)
Category ADC/DAC/Data Conversion
Pins 65

CAD (KiCad official)

  • Symbol: ADS5281IRGCR
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ads5281irgcr-etched.step / ads5281irgcr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads5281irgcr.step / ads5281irgcr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 b793bc6b7365edb1, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF