component
A6985F
Public Made by Adomby adom
STMicroelectronics DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownA6985F
STMicroelectronics · DC-DC Converters · TSSOP-16-EP
A6985F from STMicroelectronics, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RST | output | Open-collector reset output that is driven low when the output voltage is out of regulation and released after the adjustable DELAY once VOUT is above the active delay threshold. |
| 2 | VCC | power_out | Internal LDO output that supplies the embedded analog circuitry; connect a ceramic capacitor of at least 470 nF to filter the internal voltage reference. |
| 3 | SS/INH | bidirectional | Soft-start and inhibit node: an open-collector stage clamping this pin to GND disables the device, and an internal current generator (4 µA typ.) charges the external soft-start capacitor. |
| 4 | SYNCH/ISKP | input | Master/slave synchronization input in LNM and current-level skip select in LCM; leave floating when not used in LNM. |
| 5 | FSW | input | Switching frequency strap: a pull-up resistor (E24 series) to VCC or pull-down to GND selects fSW, and pinstrapping is active only before the soft-start phase. |
| 6 | MLF | input | Strap pin: a pull-up (E24 series) to VCC or pull-down to GND selects low noise or low consumption mode and the active RST threshold, active only before the soft-start phase. |
| 7 | COMP | passive | Output of the error amplifier, where the designed compensation network is connected. |
| 8 | DELAY | passive | An external capacitor sets the delay before RST is released after VOUT exceeds the reset threshold; if left floating, RST behaves like a power good. |
| 9 | VOUT | input | Output voltage sensing input. |
| 10 | SGND | power_in | Signal ground; the exposed pad must be connected to SGND and PGND. |
| 11 | PGND | power_in | Power ground for the output power stage. |
| 12 | PGND | power_in | Power ground for the output power stage. |
| 13 | LX | output | Switching node of the power stage; absolute maximum range is -0.3 V to VIN + 0.3 V. |
| 14 | LX | output | Switching node of the power stage; absolute maximum range is -0.3 V to VIN + 0.3 V. |
| 15 | VIN | power_in | DC input voltage, 4 V to 38 V operating range with an absolute maximum of 40 V. |
| 16 | VBIAS | power_in | Typically connected to the regulated output to supply part of the analog circuitry for better light-load efficiency; connect to GND if not used, with absolute maximum of (VIN + 0.3) or 6 V. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | TSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
A6985F - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
a6985f-etched.step/a6985f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);a6985f.step/a6985f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (83 pp, sha256
e0ef199622516f28, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).