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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

A6986ITR

STMicroelectronics · DC-DC Converters · HTSSOP-16

A6986ITR from STMicroelectronics, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RST	output	Open-collector reset output that is driven low when the output voltage is out of regulation and is released after the DELAY time once the primary output is over the active delay threshold.
2	VCC	power_out	Internal regulated reference rail that must be filtered with a ceramic capacitor of at least 470 nF and supplies the embedded analog circuitry.
3	SS / INH	bidirectional	Open-collector inhibit input that disables the device when clamped to GND, and soft-start pin charged by an internal 4 µA typical current generator through an external capacitor.
4	SYNCH	input	Master/slave synchronization pin that must be left floating when synchronization is not used.
5	FSW	input	Switching frequency selection pin, set by a E24-series pull-up to VCC or pull-down to GND, with the strapping active only before the soft-start phase.
6	MLF	input	Connect to ground directly or through a pull-down resistor to adjust the RST threshold as defined in Table 7.
7	COMP	passive	Output of the error amplifier, where the designed compensation network is connected.
8	DELAY	passive	An external capacitor sets the RST rising-edge delay after the output exceeds the reset threshold; if left floating, RST behaves like a Power Good.
9	FB	input	Primary output voltage sensing input.
10	SGND	power_in	Signal ground, which must be connected to the exposed pad.
11	PGND	power_in	Power ground, which must be connected to the exposed pad.
12	PGND	power_in	Power ground, which must be connected to the exposed pad.
13	LX	output	Switching node; absolute maximum voltage is VIN + 0.3 V (LX rated -0.3 V to VIN + 0.3 V).
14	LX	output	Switching node; absolute maximum voltage is VIN + 0.3 V (LX rated -0.3 V to VIN + 0.3 V).
15	VIN	power_in	DC input voltage, rated -0.3 V to 40 V absolute maximum, with a 4 V to 38 V operating input range.
16	VBIAS	power_in	Typically connected to the regulated primary output if it does not exceed 6 V; otherwise connect it to GND.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-16
Category	Power Management (PMIC)
Pins	17

CAD (KiCad official)

Symbol: A6986ITR
Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-16 (KiCad packages3D, STEP)
3D model files: a6986itr-etched.step / a6986itr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); a6986itr.step / a6986itr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (62 pp, sha256 1f7f6ab7d7f12bca, retrieved 2026-10-07, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF