component
LM-LM61089B
Public Unreviewedby Ray
Leiditech Semiconductor Discharge Tubes (TSS), SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads when scrolled away or the tab is hidden.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
PCB Footprint
Open full view ↗Loads on click. Unloads when scrolled away or the tab is hidden.
Datasheet
Open in new tab ↗Loads on click. Unloads when scrolled away or the tab is hidden.
README
markdownLM-LM61089B
Leiditech · Semiconductor Discharge Tubes (TSS) · SOP-8
LM-LM61089B from Leiditech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K1 | passive | Cathode 1 (Tip). Connects to the Tip line conductor of the protected pair. Acts as the cathode of the first thyristor/diode protection channel referenced to the gate. |
| 2 | G | passive | Gate terminal. Programmable gate reference input, typically connected to the SLIC negative supply (VBATH) via a 220nF decoupling capacitor. Sets the negative protection voltage threshold; IGT=5mA max, VGT=2.5V max. |
| 3 | NC | unconnected | No internal connection. Leave floating or tie to any potential. |
| 4 | K2 | passive | Cathode 2 (Ring). Connects to the Ring line conductor of the protected pair. Acts as the cathode of the second thyristor/diode protection channel referenced to the gate. |
| 5 | K2 | passive | Cathode 2 (Ring) - internally bonded to pin 4 for lower parasitic inductance in the '4-point' wire bonding configuration. |
| 6 | A | passive | Anode (Ground). Common anode of both protection channels; connects to circuit ground / 0V reference. Positive overvoltages are clipped by the anti-parallel diodes to this node. |
| 7 | A | passive | Anode (Ground) - internally bonded to pin 6 for reduced parasitic inductance. Connect to circuit ground / 0V reference. |
| 8 | K1 | passive | Cathode 1 (Tip) - internally bonded to pin 1 for reduced parasitic inductance in the '4-point' bonding configuration. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | SOP-8 |
| Category | Circuit Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
LM-LM61089B - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leiditech datasheet (11 pp, sha256
168cfce0bf1b3557, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).