component
SI8610EC-B-IS
Public Made by Adomby adom
Skyworks Solutions Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSI8610EC-B-IS
Skyworks Solutions · Digital Isolators · SOIC-8
SI8610EC-B-IS from Skyworks Solutions, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Side 1 power supply, operating range 2.5-5.5 V, requires a 0.1 µF bypass capacitor to GND1 placed close to the package. |
| 2 | A1 | input | Side 1 digital input (Si8610 has one channel with its input on the VDD1 side) with Schmitt trigger input. |
| 3 | NC | unconnected | Listed as VDD1/NC for Si861x; not internally connected and can be left floating, tied to VDD, or tied to GND. |
| 4 | GND1 | power_in | Side 1 ground. |
| 5 | GND2 | power_in | Side 2 ground. |
| 6 | B1 | output | Side 2 digital output of the single channel, with a nominal output impedance of about 50 Ω ±40%. |
| 7 | NC | unconnected | Listed as GND2/NC for Si861x; not internally connected and can be left floating, tied to VDD, or tied to GND. |
| 8 | VDD2 | power_in | Side 2 power supply, operating range 2.5-5.5 V, requires a 0.1 µF bypass capacitor to GND2 placed close to the package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Skyworks Solutions |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Undervoltage Threshold (rising) | VDDUV+ | 1.95 | 2.24 | 2.375 | V | VDD1, VDD2 rising | 11 |
| VDD Undervoltage Threshold (falling) | VDDUV- | 1.88 | 2.16 | 2.325 | V | VDD1, VDD2 falling | 11 |
| VDD Undervoltage Hysteresis | VDDHYS | 50 | 70 | 95 | mV | 11 | |
| Positive-Going Input Threshold | VT+ | 1.4 | 1.67 | 1.9 | V | All inputs rising | 11 |
| Negative-Going Input Threshold | VT- | 1 | 1.23 | 1.4 | V | All inputs falling | 11 |
| Input Hysteresis | VHYS | 0.38 | 0.44 | 0.5 | V | 11 | |
| High Level Input Voltage | VIH | 2 | V | 11 | |||
| Low Level Input Voltage | VIL | 0.8 | V | 11 | |||
| High Level Output Voltage (5 V table) | VOH | 4.8 | V | loh = -4 mA; min printed as VDD1, VDD2, 0.4; VDD = 5 V ±10% | 11 | ||
| Low Level Output Voltage | VOL | 0.2 | 0.4 | V | lol = 4 mA | 11 | |
| Input Leakage Current Si86xxxB/C/D | IL | -10 | 10 | µA | Si86xxxB/C/D | 11 | |
| Output Impedance | ZO | 50 | Ω | 11 | |||
| Si8610 DC Supply Current VDD1, VI = 0(Bx), 1(Ex) | IDD1 | 0.6 | 1.2 | mA | All inputs 0 V or at supply; VI = 0(Bx), 1(Ex) | 11 | |
| Si8610 DC Supply Current VDD2, VI = 0(Bx), 1(Ex) | IDD2 | 0.8 | 1.5 | mA | All inputs 0 V or at supply; VI = 0(Bx), 1(Ex) | 11 | |
| Si8610 DC Supply Current VDD1, VI = 1(Bx), 0(Ex) | IDD1 | 1.8 | 2.9 | mA | All inputs 0 V or at supply; VI = 1(Bx), 0(Ex) | 11 | |
| Si8610 DC Supply Current VDD2, VI = 1(Bx), 0(Ex) | IDD2 | 0.8 | 1.5 | mA | All inputs 0 V or at supply; VI = 1(Bx), 0(Ex) | 11 | |
| Si8610 1 Mbps Supply Current VDD1 | IDD1 | 1.2 | 2 | mA | All inputs = 500 kHz square wave, CL = 15 pF on all outputs | 12 | |
| Si8610 1 Mbps Supply Current VDD2 | IDD2 | 0.9 | 1.5 | mA | All inputs = 500 kHz square wave, CL = 15 pF on all outputs | 12 | |
| Si8610 10 Mbps Supply Current VDD1 | IDD1 | 1.2 | 2 | mA | All inputs = 5 MHz square wave, CL = 15 pF on all outputs | 12 | |
| Si8610 10 Mbps Supply Current VDD2 (5 V table) | IDD2 | 1.2 | 2 | mA | All inputs = 5 MHz square wave, CL = 15 pF on all outputs; VDD = 5 V ±10% | 12 | |
| Si8610 100 Mbps Supply Current VDD1 | IDD1 | 1.2 | 2 | mA | All inputs = 50 MHz square wave, CL = 15 pF on all outputs | 13 | |
| Si8610 100 Mbps Supply Current VDD2 (5 V table) | IDD2 | 4.8 | 6.7 | mA | All inputs = 50 MHz square wave, CL = 15 pF on all outputs; VDD = 5 V ±10% | 13 | |
| Data Rate | 0 | 150 | Mbps | 13 | |||
| Minimum Pulse Width | 5 | ns | 13 | ||||
| Propagation Delay (5 V and 3.3 V tables) | tPHL, tPLH | 5 | 8 | 13 | ns | See Figure 4.1 Propagation Delay Timing | 13 |
| Pulse Width Distortion (5 V and 3.3 V tables) | PWD | 0.2 | 4.5 | ns | /tPLH, tPHL/; See Figure 4.1 Propagation Delay Timing | 13 | |
| Propagation Delay Skew (5 V and 3.3 V tables) | tPSK(P-P) | 2 | 4.5 | ns | 13 | ||
| Channel-Channel Skew | tPSK | 0.4 | 2.5 | ns | 13 | ||
| Output Rise Time | tr | 2.5 | 4 | ns | CL = 15 pF; See Figure 4.1 | 14 | |
| Output Fall Time | tf | 2.5 | 4 | ns | CL = 15 pF; See Figure 4.1 | 14 | |
| Peak Eye Diagram Jitter | tJIT(PK) | 350 | ps | See Figure 2.3 Eye Diagram | 14 | ||
| Common Mode Transient Immunity Si86xxxB/C/D | CMTI | 35 | 50 | kV/µs | VI = VDD or 0 V, VCM = 1500 V; Si86xxxB/C/D | 14 | |
| Start-up Time | tSU | 15 | 40 | µs | 14 | ||
| High Level Output Voltage (3.3 V table) | VOH | 3.1 | V | loh = -4 mA; min printed as VDD1, VDD2, 0.4; VDD = 3.3 V ±10% | 16 | ||
| Si8610 10 Mbps Supply Current VDD2 (3.3 V table) | IDD2 | 1 | 1.8 | mA | All inputs = 5 MHz square wave, CL = 15 pF on all outputs; VDD = 3.3 V ±10% | 17 | |
| Si8610 100 Mbps Supply Current VDD2 (3.3 V table) | IDD2 | 3.4 | 5.1 | mA | All inputs = 50 MHz square wave, CL = 15 pF on all outputs; VDD = 3.3 V ±10% | 17 | |
| High Level Output Voltage (2.5 V table) | VOH | 2.3 | V | loh = -4 mA; min printed as VDD1, VDD2, 0.4; VDD = 2.5 V ±5% | 19 | ||
| Si8610 10 Mbps Supply Current VDD2 (2.5 V table) | IDD2 | 1 | 1.6 | mA | All inputs = 5 MHz square wave, CL = 15 pF on all outputs; VDD = 2.5 V ±5% | 20 | |
| Si8610 100 Mbps Supply Current VDD2 (2.5 V table) | IDD2 | 2.7 | 4.4 | mA | All inputs = 50 MHz square wave, CL = 15 pF on all outputs; VDD = 2.5 V ±5% | 21 | |
| Propagation Delay (2.5 V table) | tPHL, tPLH | 5 | 8 | 14 | ns | See Figure 4.1 Propagation Delay Timing; VDD = 2.5 V ±5% | 21 |
| Pulse Width Distortion (2.5 V table) | PWD | 0.2 | 5 | ns | /tPLH, tPHL/; See Figure 4.1; VDD = 2.5 V ±5% | 21 | |
| Propagation Delay Skew (2.5 V table) | tPSK(P-P) | 2 | 5 | ns | VDD = 2.5 V ±5% | 21 | |
| Supply Voltage VDD1 | VDD1 | 2.5 | 5.5 | V | 11 | ||
| Supply Voltage VDD2 | VDD2 | 2.5 | 5.5 | V | 11 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 27 | ||
| Operating Temperature | TA | -40 | 125 | °C | 27 | ||
| Junction Temperature | TJ | 150 | °C | 27 | |||
| Supply Voltage | VDD1, VDD2 | -0.5 | 7 | V | 27 | ||
| Input Voltage | VI | -0.5 | V | max printed as VDD + 0.5 V | 27 | ||
| Output Voltage | VO | -0.5 | V | max printed as VDD + 0.5 V | 27 | ||
| Output Current Drive Channel | IO | 10 | mA | 27 | |||
| Lead Solder Temperature | 260 | °C | 10 s | 27 | |||
| Maximum Isolation (Input to Output), SOIC-8 | 4500 | VRMS | 1 sec; SOIC-8 & DFN-8 | 27 | |||
| IC Junction-to-Air Thermal Resistance, SOIC-8 | θJA | 140 | °C/W | SOIC-8 | 26 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. | 37 |
CAD (KiCad official)
- Symbol:
SI8610EC-B-IS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
si8610ec-b-is-etched.step/si8610ec-b-is-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si8610ec-b-is.step/si8610ec-b-is.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Skyworks Solutions datasheet (43 pp, sha256
e131307ab2df36e4, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).