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TLC2543IDBR
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Texas Instruments Analog To Digital Converters (ADC), SSOP-20-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTLC2543IDBR
Texas Instruments · Analog To Digital Converters (ADC) · SSOP-20-208mil
TLC2543IDBR from Texas Instruments, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN0 | input | Analog input AIN0 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 2 | AIN1 | input | Analog input AIN1 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 3 | AIN2 | input | Analog input AIN2 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 4 | AIN3 | input | Analog input AIN3 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 5 | AIN4 | input | Analog input AIN4 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 6 | AIN5 | input | Analog input AIN5 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 7 | AIN6 | input | Analog input AIN6 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 8 | AIN7 | input | Analog input AIN7 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 9 | AIN8 | input | Analog input AIN8 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 10 | GND | power_in | Ground is the ground return terminal for the internal circuitry, and all voltage measurements are made with respect to GND. |
| 11 | AIN9 | input | Analog input AIN9 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 12 | AIN10 | input | Analog input AIN10 is one of 11 internally multiplexed analog inputs, and its driving source impedance should be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and capable of slewing into 60 pF. |
| 13 | REF- | input | Negative reference voltage, nominally ground, is applied to REF- and sets the lower end of the input range. |
| 14 | REF+ | input | Positive reference voltage, nominally VCC, is applied to REF+, and the maximum input range is the difference between REF+ and REF-. |
| 15 | CS | input | Chip select: a high-to-low transition resets the internal counters and controls and enables DATA OUT, DATA INPUT and I/O CLOCK, and a low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. |
| 16 | DATA OUT | tri_state | The 3-state serial output carries the A/D conversion result, is in high impedance when CS is high and active when CS is low, and changes on the falling edge of I/O CLOCK. |
| 17 | DATA INPUT | input | Serial data input: a 4-bit MSB-first address selects the analog input or test voltage to convert next, shifted in on the first four rising edges of I/O CLOCK. |
| 18 | I/O CLOCK | input | Input/output clock clocks the input data in on the rising edges, shifts the previous conversion data out on DATA OUT on the falling edges, and transfers conversion control to the internal state controller on the falling edge of the last I/O CLOCK. |
| 19 | EOC | output | End of conversion goes low after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer. |
| 20 | VCC | power_in | Positive supply voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-20-208mil |
| Category | Data Acquisition |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
TLC2543IDBR - Footprint:
Package_SO:SSOP-20_5.3x7.2mm_P0.65mm - 3D model: SSOP-20-208mil (KiCad packages3D, STEP)
- 3D model files:
tlc2543idbr-etched.step/tlc2543idbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlc2543idbr.step/tlc2543idbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
4f0ece16b966081b, retrieved 2026-10-12, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).