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TL16C2550RHBR

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Texas Instruments UART, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232tl16c2550rhbrfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TL16C2550RHBR

Texas Instruments · UART · VQFN-32-EP(5x5)

TL16C2550RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D6 bidirectional Data bus bit 6 for 8-bit parallel CPU interface.
2 D7 bidirectional Data bus bit 7 for 8-bit parallel CPU interface.
3 RXB input Serial receive data input for UART channel B.
4 RXA input Serial receive data input for UART channel A.
5 TXA output Serial transmit data output for UART channel A.
6 TXB output Serial transmit data output for UART channel B.
7 CSA input Active-low chip select for UART channel A enabling register access.
8 CSB input Active-low chip select for UART channel B enabling register access.
9 NC unconnected No internal connection.
10 XTAL1 input Crystal oscillator input or external clock input for frequencies 1 to 24 MHz.
11 XTAL2 output Crystal oscillator output or buffered external clock output.
12 IOW input Write input (active-low strobe) transfers data bus contents to internal register.
13 GND power_in Signal and power ground (0 V reference).
14 IOR input Read input (active-low strobe) loads internal register contents onto data bus.
15 RTSB output Active-low request to send output for channel B hardware flow control.
16 CTSB input Active-low clear to send input for channel B hardware flow control.
17 NC unconnected No internal connection.
18 A2 input Address select bit 2 for internal register address selection.
19 A1 input Address select bit 1 for internal register address selection.
20 A0 input Address select bit 0 for internal register address selection.
21 INTA output Active-high interrupt output for UART channel A.
22 INTB output Active-high interrupt output for UART channel B.
23 RTSA output Active-low request to send output for channel A hardware flow control.
24 RESET input Active-high reset input clears all registers and disables transmitter and receiver.
25 CTSA input Active-low clear to send input for channel A hardware flow control.
26 VCC power_in Power supply voltage (1.8 V to 5 V nominal).
27 D0 bidirectional Data bus bit 0 (least significant bit) for parallel CPU interface.
28 D1 bidirectional Data bus bit 1 for parallel CPU interface.
29 D2 bidirectional Data bus bit 2 for parallel CPU interface.
30 D3 bidirectional Data bus bit 3 for parallel CPU interface.
31 D4 bidirectional Data bus bit 4 for parallel CPU interface.
32 D5 bidirectional Data bus bit 5 for parallel CPU interface.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Communication Interface Chip/UART/485/232
Pins 33

CAD (KiCad official)

  • Symbol: TL16C2550RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: tl16c2550rhbr-etched.step / tl16c2550rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl16c2550rhbr.step / tl16c2550rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (49 pp, sha256 27f2cc28a5ba3ac9, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF