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ADS1217IPFBR

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Texas Instruments Analog To Digital Converters (ADC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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ADS1217IPFBR

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-48(7x7)

ADS1217IPFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog power supply input; the datasheet specifies AVDD at 4.75 V to 5.25 V for 5 V operation and 2.7 V to 3.3 V for 3 V operation.
2 AGND power_in Analog ground return for the analog circuitry.
3 AIN0 passive Analog input channel 0 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
4 AIN1 passive Analog input channel 1 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
5 AIN2 passive Analog input channel 2 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
6 AIN3 passive Analog input channel 3 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
7 AIN4 passive Analog input channel 4 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
8 AIN5 passive Analog input channel 5 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
9 AIN6 passive Analog input channel 6 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
10 AIN7 passive Analog input channel 7 of the 8-channel multiplexer; with the buffer on, the input range is AGND + 0.05 V to AVDD - 1.5 V.
11 AINCOM passive Analog input common connection for the multiplexed analog inputs.
12 AGND power_in Analog ground return for the analog circuitry.
13 AVDD power_in Analog power supply input; the datasheet specifies AVDD at 4.75 V to 5.25 V for 5 V operation and 2.7 V to 3.3 V for 3 V operation.
14 VRCAP passive Bypass capacitor connection for the on-chip VREFOUT reference.
15 IDAC1 output Current DAC 1 output; the full-scale current is set by the RDAC resistor (0.5 mA to 2 mA at RDAC = 150 kΩ, per range).
16 IDAC2 output Current DAC 2 output; the full-scale current is set by the RDAC resistor (0.5 mA to 2 mA at RDAC = 150 kΩ, per range).
17 RDAC passive Current DAC setting resistor connection; the datasheet specifies RDAC between 10 kΩ and the value used to set the IDAC full-scale current.
18 DGND power_in Digital ground return for the digital circuitry.
19 DGND power_in Digital ground return for the digital circuitry.
20 DGND power_in Digital ground return for the digital circuitry.
21 DGND power_in Digital ground return for the digital circuitry.
22 DGND power_in Digital ground return for the digital circuitry.
23 BUFEN input Buffer enable input that selects the high-input-impedance analog input buffer.
24 RESET input Active LOW input that resets the entire chip.
25 XIN input Clock input for the master clock (crystal or resonator, or external clock; master clock range 1 MHz to 8 MHz).
26 XOUT output Clock output used with a crystal or resonator.
27 PDWN input Active LOW power-down input that shuts down the analog and digital circuits.
28 POL input Serial clock polarity input for the SPI interface.
29 DSYNC input Active LOW synchronization control input.
30 DGND power_in Digital ground return for the digital circuitry.
31 DVDD power_in Digital power supply input; the datasheet specifies DVDD from 2.7 V to 5.25 V.
32 DRDY output Active LOW data ready output that indicates a new conversion result is available.
33 CS input Active LOW chip select input for the serial interface (may be tied LOW).
34 SCLK input Serial clock input with Schmitt-trigger input; SCLK pulse width HIGH and LOW must be at least 200 ns.
35 DIN input Serial data input with Schmitt-trigger input; data must be set up and held around the SCLK edge (50 ns minimum each).
36 DOUT output Serial data output; goes tri-state immediately when CS goes HIGH.
37 D0 bidirectional Digital I/O bit 0, usable as input or output.
38 D1 bidirectional Digital I/O bit 1, usable as input or output.
39 D2 bidirectional Digital I/O bit 2, usable as input or output.
40 D3 bidirectional Digital I/O bit 3, usable as input or output.
41 D4 bidirectional Digital I/O bit 4, usable as input or output.
42 D5 bidirectional Digital I/O bit 5, usable as input or output.
43 D6 bidirectional Digital I/O bit 6, usable as input or output.
44 D7 bidirectional Digital I/O bit 7, usable as input or output.
45 AGND power_in Analog ground return for the analog circuitry.
46 VREFOUT output On-chip voltage reference output (1.25 V or 2.5 V, selected by REF HI).
47 VREF+ power_in Positive differential reference input; the reference input VREF (VREF+ minus VREF-) is specified from 0.1 V to 2.6 V.
48 VREF- power_in Negative differential reference input; specified from AGND - 0.1 V to (VREF+) - 0.1 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Data Acquisition
Pins 48

CAD (KiCad official)

  • Symbol: ADS1217IPFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ads1217ipfbr-etched.step / ads1217ipfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1217ipfbr.step / ads1217ipfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 0a2b6af4651a91dd, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF