component
ULN2003AFWG
Public Made by Adomby adom
TOSHIBA Darlington Transistor Arrays, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownULN2003AFWG
TOSHIBA · Darlington Transistor Arrays · SOIC-16
ULN2003AFWG from TOSHIBA, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I1 | input | Input channel 1 for Darlington pair 1; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 2 | I2 | input | Input channel 2 for Darlington pair 2; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 3 | I3 | input | Input channel 3 for Darlington pair 3; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 4 | I4 | input | Input channel 4 for Darlington pair 4; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 5 | I5 | input | Input channel 5 for Darlington pair 5; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 6 | I6 | input | Input channel 6 for Darlington pair 6; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 7 | I7 | input | Input channel 7 for Darlington pair 7; TTL/5 V CMOS compatible, VIN(ON) min 2.8 V, VIN(OFF) max 0.7 V, VIN absolute max 24 V. |
| 8 | GND | power_in | Common emitter ground return for all seven NPN Darlington pairs; connect to system ground. |
| 9 | COMMON | passive | Clamp diode cathode bus; connect to inductive load supply (VCE(SUS) max 50 V, IF max 500 mA) for flyback suppression; may be left open when clamp diodes are not used. |
| 10 | O7 | tri_state | Open-collector NPN Darlington output channel 7 (paired with I7); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
| 11 | O6 | tri_state | Open-collector NPN Darlington output channel 6 (paired with I6); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
| 12 | O5 | tri_state | Open-collector NPN Darlington output channel 5 (paired with I5); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
| 13 | O4 | tri_state | Open-collector NPN Darlington output channel 4 (paired with I4); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
| 14 | O3 | tri_state | Open-collector NPN Darlington output channel 3 (paired with I3); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
| 15 | O2 | tri_state | Open-collector NPN Darlington output channel 2 (paired with I2); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
| 16 | O1 | tri_state | Open-collector NPN Darlington output channel 1 (paired with I1); IOUT max 500 mA, VCE(SUS) max 50 V, VCE(sat) typ 1.1 V at IOUT = 200 mA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOIC-16 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
ULN2003AFWG - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
uln2003afwg-etched.step/uln2003afwg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);uln2003afwg.step/uln2003afwg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (11 pp, sha256
117c2ac6e3d676f9, retrieved 2026-09-29, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).