ADUM262N1WBRIZ from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Supply voltage for isolator side 1, operating range 1.7 V to 5.5 V.
2	VIA	input	Logic input A.
3	VIB	input	Logic input B.
4	VIC	input	Logic input C.
5	VID	input	Logic input D.
6	VOE	output	Logic output E.
7	VOF	output	Logic output F.
8	GND1	power_in	Ground 1, ground reference for isolator side 1.
9	GND2	power_in	Ground 2, ground reference for isolator side 2.
10	VIF	input	Logic input F.
11	VIE	input	Logic input E.
12	VOD	output	Logic output D.
13	VOC	output	Logic output C.
14	VOB	output	Logic output B.
15	VOA	output	Logic output A.
16	VDD2	power_in	Supply voltage for isolator side 2, operating range 1.7 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-16
Category	Signal Isolation Devices
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Propagation Delay (5 V)	tPHL, tPLH	4.8	7.2	13	ns	50% input to 50% output; 4.5 V ≤ VDDx ≤ 5.5 V	4
Pulse Width Distortion (5 V)	PWD		0.5	4.5	ns	/tPLH − tPHL/	4
Propagation Delay Skew (5 V)	tPSK			6.1	ns	Between any two units at the same temperature, voltage, and load	4
Channel Matching Codirectional (5 V)	tPSKCD		0.5	4	ns		4
Channel Matching Opposing Direction (5 V)	tPSKOD		0.5	4.5	ns		4
Pulse Width	PW			6.6	ns	Within pulse width distortion (PWD) limit	4
Data Rate		150			Mbps	Within PWD limit	4
Input Threshold Voltage Logic High	VIH	0.7			× VDDx		4
Input Threshold Voltage Logic Low	VIL			0.3	× VDDx		4
Output Voltage Logic Low (5 V)	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	4
Output Voltage Logic Low (5 V)	VOL		0.2	0.4	V	IOx = 4 mA, VIx = VIxL	4
Input Current per Channel	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	4
Quiescent Supply Current Side 1 (5 V)	IDD1 (Q)		2.8	4	mA	VI = 1 (N1)	4
Quiescent Supply Current Side 2 (5 V)	IDD2 (Q)		3	4.2	mA	VI = 1 (N1)	4
Common-Mode Transient Immunity, high	/CMH/	75	100		kV/µs	VIx = VDDx, VCM = 1000 V, transient magnitude = 800 V	5
Common-Mode Transient Immunity, low	/CML/	75	100		kV/µs	VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V	5
Propagation Delay (3.3 V)	tPHL, tPLH	4.8	6.8	14	ns	50% input to 50% output; 3.0 V ≤ VDDx ≤ 3.6 V	6
Pulse Width Distortion (3.3 V)	PWD		0.7	4.5	ns	/tPLH − tPHL/	6
Quiescent Supply Current Side 1 (3.3 V)	IDD1 (Q)		2.6	3.8	mA	VI = 1 (N1)	6
Quiescent Supply Current Side 2 (3.3 V)	IDD2 (Q)		2.8	4	mA	VI = 1 (N1)	6
Propagation Delay (2.5 V)	tPHL, tPLH	5	7	14	ns	50% input to 50% output; 2.25 V ≤ VDDx ≤ 2.75 V	8
Pulse Width Distortion (2.5 V)	PWD		0.7	5	ns	/tPLH − tPHL/	8
Quiescent Supply Current Side 1 (2.5 V)	IDD1 (Q)		2.5	3.7	mA	VI = 1 (N1)	8
Quiescent Supply Current Side 2 (2.5 V)	IDD2 (Q)		2.7	3.9	mA	VI = 1 (N1)	8
Propagation Delay (1.8 V)	tPHL, tPLH	5.8	8.7	15	ns	50% input to 50% output; 1.7 V ≤ VDDx ≤ 1.9 V	10
Pulse Width Distortion (1.8 V)	PWD		0.7	5	ns	/tPLH − tPHL/	10
Quiescent Supply Current Side 1 (1.8 V)	IDD1 (Q)		2.4	3.6	mA	VI = 1 (N1)	10
Quiescent Supply Current Side 2 (1.8 V)	IDD2 (Q)		2.7	3.9	mA	VI = 1 (N1)	10
Dynamic Input Supply Current (5 V)	IDDI (D)		0.01		mA/Mbps	Inputs switching, 50% duty cycle	5
Dynamic Output Supply Current (5 V)	IDDO (D)		0.02		mA/Mbps	Inputs switching, 50% duty cycle	5
Positive VDDx UVLO Threshold	VDDxUV+		1.6		V		5
Negative VDDx UVLO Threshold	VDDxUV−		1.5		V		5
VDDx Hysteresis	VDDxUVH		0.1		V		5
Output Rise/Fall Time	tR/tF		2.5		ns	10% to 90%	5
Change in Propagation Delay vs. Temperature			1.5		ps/°C		4
Operating Temperature	TA	-40		125	°C		15
Supply Voltages	VDD1, VDD2	1.7		5.5	V		15
Input Signal Rise and Fall Times				1	ms		15
Storage Temperature Range	TST	-65		150	°C	TA = 25°C	16
Ambient Operating Temperature Range	TA	-40		125	°C	TA = 25°C	16
Supply Voltages	VDD1, VDD2	-0.5		7	V		16
Side 1 Average Output Current per Pin	IO1	-10		10	mA		16
Side 2 Average Output Current per Pin	IO2	-10		10	mA		16
Common-Mode Transients		-150		150	kV/µs	Across the insulation barrier	16
IC Junction to Ambient Thermal Resistance	θJA		45		°C/W	Thermocouple located at center of package underside	12
Capacitance (Input to Output)	CI-O		2.2		pF	f = 1 MHz	12
Input Capacitance	CI		4		pF		12
Rated Dielectric Insulation Voltage			5000		VRMS	1-minute duration	12

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	pC		In accordance with DIN EN IEC 60747-17 (VDE 0884-17), each ADuM260N/ADuM261N/ADuM262N/ADuM263N in the RI-16 wide body (SOIC_IC) package is proof tested by applying an insulation test voltage ≥ 1592 VP	13

CAD (KiCad official)

Symbol: ADUM262N1WBRIZ
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: adum262n1wbriz-etched.step / adum262n1wbriz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum262n1wbriz.step / adum262n1wbriz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (27 pp, sha256 319a4ec2345a19be, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

ADUM262N1WBRIZ

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3D Model

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