component
SLB9670VQ20FW785XTMA1
Public Unreviewedby Ray
Infineon Technologies Security Verification / Encryption ICs, QFN-32-EP(5x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSLB9670VQ20FW785XTMA1
Infineon Technologies · Security Verification / Encryption ICs · QFN-32-EP(5x5)
SLB9670VQ20FW785XTMA1 from Infineon Technologies, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NCI/VDD | passive | Not connected internally. Per TCG specification pin 1 is defined as VDD; VDD may be connected here for compliance. |
| 2 | GND | power_in | Ground pin. All GND pins must be connected externally. |
| 3 | NCI | unconnected | Not connected internally. May be connected externally. |
| 4 | NCI | unconnected | Not connected internally. May be connected externally. |
| 5 | NCI | unconnected | Not connected internally. May be connected externally. |
| 6 | GPIO | bidirectional | GPIO-Express-00 signal. Not used by the TPM2.0 device; may be left unconnected. Has internal pull-up resistor. Tri-State buffer (TS). |
| 7 | PP | input | Physical Presence input. Not used by the TPM2.0 device; may be left unconnected. Has internal pull-down resistor. Schmitt-Trigger input. |
| 8 | VDD | power_in | Power Supply pin. Operating range 3.0-3.6 V (3.3 V typ) or 1.65-1.95 V (1.8 V typ). Must be bypassed to GND via 100 nF capacitors. |
| 9 | GND | power_in | Ground pin. All GND pins must be connected externally. |
| 10 | NCI | unconnected | Not connected internally. May be connected externally. |
| 11 | NCI | unconnected | Not connected internally. May be connected externally. |
| 12 | NCI | unconnected | Not connected internally. May be connected externally. |
| 13 | NCI | unconnected | Not connected internally. May be connected externally. |
| 14 | NCI/VDD | power_in | Not connected internally. Per TCG specification pin 14 is defined as VDD; VDD must be connected here for compliance and upwards compatibility to future TPMs. |
| 15 | NCI | unconnected | Not connected internally. May be connected externally. |
| 16 | NCI/GND | passive | Not connected internally. Per TCG specification pin 16 is defined as GND; GND may be connected here for compliance. |
| 17 | RST# | input | External Reset signal (active low). Asserting unconditionally resets the device; typically connected to the host PCIRST#. Weak internal pull-up. Schmitt-Trigger input. |
| 18 | PIRQ# | output | Interrupt Request signal to the host (active low). Open-drain output; no internal pull-up resistor - external pull-up required. |
| 19 | SCLK | input | SPI Clock input. Only SPI mode 0 is supported. Max clock 43 MHz at VDD=3.3 V. Schmitt-Trigger input. |
| 20 | CS# | input | SPI Chip Select input (active low). Schmitt-Trigger input. |
| 21 | MOSI | input | Master Out Slave In. SPI data received from the master. Schmitt-Trigger input. |
| 22 | VDD | power_in | Power Supply pin. Operating range 3.0-3.6 V (3.3 V typ) or 1.65-1.95 V (1.8 V typ). Must be bypassed to GND via 100 nF capacitors. |
| 23 | GND | power_in | Ground pin. All GND pins must be connected externally. |
| 24 | MISO | output | Master In Slave Out. SPI data sent to the SPI bus master. Tri-State output. |
| 25 | NCI | unconnected | Not connected internally. May be connected externally. |
| 26 | NCI | unconnected | Not connected internally. May be connected externally. |
| 27 | NCI | unconnected | Not connected internally. May be connected externally. |
| 28 | NCI | unconnected | Not connected internally. May be connected externally. |
| 29 | NC | unconnected | No Connect. Must be left floating (not connected externally). |
| 30 | NC | unconnected | No Connect. Must be left floating (not connected externally). |
| 31 | NCI | unconnected | Not connected internally. May be connected externally. |
| 32 | GND | power_in | Ground pin. All GND pins must be connected externally. Also refer to exposed pad which is internally connected to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | QFN-32-EP(5x5) |
| Category | Interface |
| Pins | 32 |
Ordering variants
Same part, different packaging or reel option.
SLB9670VQ20FW785XTMA1SLB 9670VQ2.0SLB9670VQ20FW785XTMA1SLB 9670XQ2.0
CAD (KiCad official)
- Symbol:
SLB9670VQ20FW785XTMA1 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (21 pp, sha256
981b978c5b86d562, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).