Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

LTC3633AEUFD#TRPBF

Analog Devices · DC-DC Converters · QFN-28-EP(4x5)

LTC3633AEUFD#TRPBF from Analog Devices, in a QFN-28-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGOOD1 output Channel 1 open-drain power good output is pulled to ground when VFB1 is outside ±8% (typ) of the 0.6V reference and becomes high impedance once VFB1 is within ±5% (typ).
2 PHMODE input Phase select input: tie to ground to switch both channels in phase or to INTVCC for 180° out of phase, and do not float this pin.
3 RUN1 input Channel 1 enable pin: above 1.22V enables the channel, below 1V places it in shutdown, and it must not be floated.
4 MODE/SYNC input Mode select and external sync input: tie to ground for forced continuous operation, float or tie to INTVCC for Burst Mode operation at light load, or drive with a clock to synchronize switching.
5 RT passive Oscillator frequency program pin: a resistor between 80k and 640k from this pin to SGND sets 500kHz to 4MHz, and tying it to INTVCC defaults the switching frequency to 2MHz.
6 RUN2 input Channel 2 enable pin: above 1.22V enables the channel, below 1V places it in shutdown, and it must not be floated.
7 SGND power_in Signal ground that should have a low-noise connection to reference ground, to which the feedback divider, compensation network and RT resistor must be connected.
8 PGOOD2 output Channel 2 open-drain power good output is pulled to ground when VFB2 is outside ±8% (typ) of the 0.6V reference and becomes high impedance once VFB2 is within ±5% (typ).
9 VFB2 input Channel 2 output feedback input that compares the feedback voltage to the internal 0.6V reference and is connected to a resistor divider to set the output voltage.
10 TRACKSS2 input Channel 2 tracking and soft-start input: forcing a voltage below 0.6V makes the error amplifier servo FB to this voltage, and an internal 1.4µA pull-up from INTVCC allows a soft-start capacitor to SGND.
11 ITH2 passive Channel 2 error amplifier output and loop compensation pin, which should be connected to INTVCC to use the default internal compensation.
12 VON2 input Channel 2 on-time voltage input that sets the on-time comparator trip point, with a VON sense range of 0.6V-6V for LTC3633A (1.5V-12V for LTC3633A-1) and a nominal impedance of 140kΩ.
13 SW2 output Channel 2 switch node connecting to the external inductor, swinging from a diode voltage drop below ground up to VIN.
14 SW2 output Channel 2 switch node connecting to the external inductor, swinging from a diode voltage drop below ground up to VIN.
15 VIN2 power_in Power supply input for the channel 2 on-chip power MOSFETs, which may operate from a supply different from VIN1.
16 VIN2 power_in Power supply input for the channel 2 on-chip power MOSFETs, which may operate from a supply different from VIN1.
17 BOOST2 power_out Boosted floating driver supply for channel 2 whose bootstrap capacitor connects between this pin and SW2, with a normal swing from a diode drop below INTVCC up to VIN+INTVCC.
18 V2P5 power_out 2.5V regulator output capable of supplying 10mA that requires a minimum 1µF low-ESR ceramic bypass capacitor, or should be tied to INTVCC if unused.
19 INTVCC power_out Internal 3.3V regulator output that powers the internal drivers and control circuits and requires a minimum 1µF low-ESR ceramic decoupling capacitor to power ground.
20 BOOST1 power_out Boosted floating driver supply for channel 1 whose bootstrap capacitor connects between this pin and SW1, with a normal swing from a diode drop below INTVCC up to VIN+INTVCC.
21 VIN1 power_in Power supply input for the channel 1 on-chip power MOSFETs, which also powers the internal LDO for INTVCC.
22 VIN1 power_in Power supply input for the channel 1 on-chip power MOSFETs, which also powers the internal LDO for INTVCC.
23 SW1 output Channel 1 switch node connecting to the external inductor, swinging from a diode voltage drop below ground up to VIN.
24 SW1 output Channel 1 switch node connecting to the external inductor, swinging from a diode voltage drop below ground up to VIN.
25 VON1 input Channel 1 on-time voltage input that sets the on-time comparator trip point, with a VON sense range of 0.6V-6V for LTC3633A (1.5V-12V for LTC3633A-1) and a nominal impedance of 140kΩ.
26 ITH1 passive Channel 1 error amplifier output and loop compensation pin, which should be connected to INTVCC to use the default internal compensation.
27 TRACKSS1 input Channel 1 tracking and soft-start input: forcing a voltage below 0.6V makes the error amplifier servo FB to this voltage, and an internal 1.4µA pull-up from INTVCC allows a soft-start capacitor to SGND.
28 VFB1 input Channel 1 output feedback input that compares the feedback voltage to the internal 0.6V reference and is connected to a resistor divider to set the output voltage.
29 PGND power_in Exposed pad power ground that must be soldered to the PCB for low-impedance electrical contact to power ground and good thermal contact.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package QFN-28-EP(4x5)
Category Power Management (PMIC)
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN1 Supply Range VIN1 3.6 20 V 3
VIN2 Supply Range VIN2 1.5 20 V 3.6V < VIN1 < 20V 3
Output Voltage Range (LTC3633A) 0.6 6 V VON = VOUT 3
VFB Feedback Reference Voltage VFB 0.594 0.6 0.606 V 3
Feedback Pin Input Current IFB -30 30 nA 3
Oscillator Frequency fOSC 1.4 2 2.6 MHz VRT = INTVCC 3
Oscillator Frequency fOSC 1.7 2 2.3 MHz RT = 162k 3
Oscillator Frequency fOSC 3.4 4 4.6 MHz RT = 80.6k 3
Positive Valley Switch Current Limit ILIM 2.6 3.5 4.5 A 3
Switch Leakage Current ISW(LKG) -1 0.01 1 µA VIN = 20V, VRUN = 0V 3
VIN Overvoltage Lockout Threshold (VIN Rising) VVIN-OV 20.3 22.5 V VIN Rising 3
VIN Overvoltage Lockout Threshold (VIN Falling) VVIN-OV 21.5 22.5 V VIN Falling 3
INTVCC Voltage INTVCC 3.1 3.3 3.5 V 3.6V < VIN < 20V, 0mA Load 3
RUN Threshold Rising RUN 1.18 1.22 1.26 V Rising 3
RUN Threshold Falling RUN 0.98 1.01 1.04 V Falling 3
RUN Leakage Current IRUN -3 0 3 µA VIN = 20V 3
V2P5 Voltage V2P5 2.46 2.5 2.54 V ILOAD = 0mA to 10mA 3
PGOOD Good-to-Bad Threshold 8 10 % VFB Rising 3
PGOOD Good-to-Bad Threshold -10 -8 % VFB Falling 3
PGOOD Bad-to-Good Threshold -5 -3 % VFB Rising 3
PGOOD Bad-to-Good Threshold 3 5 % VFB Falling 3
Power Good Filter Time tPGOOD 20 40 µs 3
Internal Soft-Start Time tSS 400 700 µs 10% to 90% Rise Time 3
VFB During Tracking VFB 0.28 0.3 0.315 V TRACKSS = 0.3V 3
PHMODE Threshold Voltage VIH VPHMODE 1 V VIH 4
PHMODE Threshold Voltage VIL VPHMODE 0.3 V VIL 4
MODE/SYNC Threshold Voltage VIH VMODE/SYNC 1 V MODE VIH 4
MODE/SYNC Threshold Voltage VIL VMODE/SYNC 0.4 V MODE VIL 4
MODE/SYNC Input Current IMODE 1.5 µA MODE = 0V 4
MODE/SYNC Input Current IMODE -1.5 µA MODE = INTVCC 4
Absolute Maximum VIN1, VIN2 VIN1, VIN2 -0.3 20 V 2
Absolute Maximum PGOOD1, PGOOD2, VON1, VON2 PGOOD1, PGOOD2, VON1, VON2 -0.3 18 V 2
Absolute Maximum BOOST1, BOOST2 BOOST1, BOOST2 -0.3 23 V 2
Absolute Maximum BOOST1-SW1, BOOST2-SW2 BOOST1-SW1, BOOST2-SW2 -0.3 3.6 V 2
Absolute Maximum V2P5, INTVCC, TRACKSS1, TRACKSS2 V2P5, INTVCC, TRACKSS1, TRACKSS2 -0.3 3.6 V 2
Absolute Maximum ITH1, ITH2, RT, MODE/SYNC (upper limit printed as INTVCC + 0.3V) ITH1, ITH2, RT, MODE/SYNC -0.3 V Max = INTVCC + 0.3V 2
Absolute Maximum VFB1, VFB2, PHMODE (upper limit printed as INTVCC + 0.3V) VFB1, VFB2, PHMODE -0.3 V Max = INTVCC + 0.3V 2
Absolute Maximum RUN1, RUN2 (upper limit printed as VIN + 0.3V) RUN1, RUN2 -0.3 V Max = VIN + 0.3V 2
Operating Junction Temperature Range TJ -40 125 °C Notes 2, 3 2
Storage Temperature Range TSTG -65 150 °C 2
Junction-to-Ambient Thermal Resistance (QFN) θJA 43 °C/W 28-lead 4mm x 5mm QFN (UFD), exposed pad soldered to PCB 2

CAD (KiCad official)

  • Symbol: LTC3633AEUFD#TRPBF
  • Footprint: Package_DFN_QFN:QFN-28-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: QFN-28-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: ltc3633aeufd-trpbf-etched.step / ltc3633aeufd-trpbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc3633aeufd-trpbf.step / ltc3633aeufd-trpbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (30 pp, sha256 6b61ad8d472eb56e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF