component
CD74HC4024PWR
Public Made by Adomby adom
Texas Instruments Logic ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownCD74HC4024PWR
Texas Instruments · Logic ICs · TSSOP-14
CD74HC4024PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP | input | Clock input, advances the counter one count on each high-to-low (negative edge) transition. |
| 2 | MR | input | Master reset input, a high level resets all counter stages so all outputs go low. |
| 3 | Q7 | output | Buffered counter stage 7 output, the most significant bit of the 7-stage binary ripple counter. |
| 4 | Q6 | output | Buffered counter stage 6 output of the 7-stage binary ripple counter. |
| 5 | Q5 | output | Buffered counter stage 5 output of the 7-stage binary ripple counter. |
| 6 | Q4 | output | Buffered counter stage 4 output of the 7-stage binary ripple counter. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | NC | unconnected | No internal connection. |
| 9 | Q3 | output | Buffered counter stage 3 output of the 7-stage binary ripple counter. |
| 10 | NC | unconnected | No internal connection. |
| 11 | Q2 | output | Buffered counter stage 2 output of the 7-stage binary ripple counter. |
| 12 | Q1' | output | Buffered counter stage 1 output, the least significant bit of the 7-stage binary ripple counter. |
| 13 | NC | unconnected | No internal connection. |
| 14 | VCC | power_in | Positive supply voltage, 2 V to 6 V for HC types, with a 0.1-uF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range (HC types) | VCC | 2 | 6 | V | HC types | 4 | |
| Input rise and fall time | tt | 1000 | ns | VCC = 2 V | 4 | ||
| Input rise and fall time | tt | 500 | ns | VCC = 4.5 V | 4 | ||
| Input rise and fall time | tt | 400 | ns | VCC = 6 V | 4 | ||
| Temperature range | TA | -55 | 125 | ℃ | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input diode current | IIK | -20 | 20 | mA | For VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output diode current | IOK | -20 | 20 | mA | For VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output source or sink current per output pin | IO | -25 | 25 | mA | For VO > -0.5 V or VO < VCC + 0.5 V | 4 | |
| Continuous current through VCC or GND | -50 | 50 | mA | 4 | |||
| Junction temperature | TJ | 150 | ℃ | 4 | |||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 4 | ||
| Junction-to-ambient thermal resistance (PW, TSSOP-14) | RθJA | 113 | °C/W | PW (TSSOP) 14 pins | 4 | ||
| High level input voltage | VIH | 1.5 | V | VCC = 2 V; -55 to 125 ℃ | 5 | ||
| High level input voltage | VIH | 3.15 | V | VCC = 4.5 V; -55 to 125 ℃ | 5 | ||
| High level input voltage | VIH | 4.2 | V | VCC = 6 V; -55 to 125 ℃ | 5 | ||
| Low level input voltage | VIL | 0.5 | V | VCC = 2 V; -55 to 125 ℃ | 5 | ||
| Low level input voltage | VIL | 1.35 | V | VCC = 4.5 V; -55 to 125 ℃ | 5 | ||
| Low level input voltage | VIL | 1.8 | V | VCC = 6 V; -55 to 125 ℃ | 5 | ||
| High level output voltage, CMOS loads | VOH | 1.9 | V | IOH = -20 μA; VCC = 2 V; -55 to 125 ℃ | 5 | ||
| High level output voltage, CMOS loads | VOH | 4.4 | V | IOH = -20 μA; VCC = 4.5 V; -55 to 125 ℃ | 5 | ||
| High level output voltage, CMOS loads | VOH | 5.9 | V | IOH = -20 μA; VCC = 6 V; -55 to 125 ℃ | 5 | ||
| High level output voltage, TTL loads | VOH | 3.7 | V | IOH = -4 mA; VCC = 4.5 V; -55 to 125 ℃ | 5 | ||
| High level output voltage, TTL loads | VOH | 5.2 | V | IOH = -5.2 mA; VCC = 6 V; -55 to 125 ℃ | 5 | ||
| Low level output voltage, CMOS loads | VOL | 0.1 | V | IOL = 20 μA; VCC = 2 V; -55 to 125 ℃ | 5 | ||
| Low level output voltage, TTL loads | VOL | 0.4 | V | IOL = 4 mA; VCC = 4.5 V; -55 to 125 ℃ | 5 | ||
| Input leakage current | II | -1 | 1 | μA | VCC or GND; VCC = 6 V; -55 to 125 ℃ | 5 | |
| Quiescent device current | ICC | 8 | 160 | μA | VCC or GND; VCC = 6 V; -55 to 125 ℃ | 5 | |
| Maximum input pulse frequency | fMAX | 4 | MHz | VCC = 2 V; -55 to 125 ℃ | 6 | ||
| Maximum input pulse frequency | fMAX | 20 | MHz | VCC = 4.5 V; -55 to 125 ℃ | 6 | ||
| Maximum input pulse frequency | fMAX | 24 | MHz | VCC = 6 V; -55 to 125 ℃ | 6 | ||
| Input pulse width | tW | 120 | ns | VCC = 2 V; -55 to 125 ℃ | 6 | ||
| Input pulse width | tW | 24 | ns | VCC = 4.5 V; -55 to 125 ℃ | 6 | ||
| Input pulse width | tW | 20 | ns | VCC = 6 V; -55 to 125 ℃ | 6 | ||
| Reset removal time | tREM | 75 | ns | VCC = 2 V; -55 to 125 ℃ | 6 | ||
| Reset removal time | tREM | 15 | ns | VCC = 4.5 V; -55 to 125 ℃ | 6 | ||
| Reset removal time | tREM | 13 | ns | VCC = 6 V; -55 to 125 ℃ | 6 | ||
| Reset pulse width | tW | 120 | ns | VCC = 2 V; -55 to 125 ℃ | 6 | ||
| Reset pulse width | tW | 24 | ns | VCC = 4.5 V; -55 to 125 ℃ | 6 | ||
| Reset pulse width | tW | 20 | ns | VCC = 6 V; -55 to 125 ℃ | 6 | ||
| Propagation delay time, CP to Q1' output | tPLH, tPHL | 210 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, CP to Q1' output | tPLH, tPHL | 42 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, CP to Q1' output | tPLH, tPHL | 36 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, Qn to Qn+1 | tPLH, tPHL | 110 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, Qn to Qn+1 | tPLH, tPHL | 22 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, Qn to Qn+1 | tPLH, tPHL | 19 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, MR to Qn | tPLH, tPHL | 255 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, MR to Qn | tPLH, tPHL | 51 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 | ||
| Propagation delay time, MR to Qn | tPLH, tPHL | 43 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 | ||
| Output transition time | tTLH, tTHL | 110 | ns | CL = 50 pF; VCC = 2 V; -55 to 125 ℃ | 7 | ||
| Output transition time | tTLH, tTHL | 22 | ns | CL = 50 pF; VCC = 4.5 V; -55 to 125 ℃ | 7 | ||
| Output transition time | tTLH, tTHL | 19 | ns | CL = 50 pF; VCC = 6 V; -55 to 125 ℃ | 7 |
CAD (KiCad official)
- Symbol:
CD74HC4024PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hc4024pwr-etched.step/cd74hc4024pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc4024pwr.step/cd74hc4024pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
05a8d24d327d36ff, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).