component
TPH1R403NL1
Public Made by Adomby adom
TOSHIBA MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPH1R403NL1
TOSHIBA · MOSFETs · SOP-8
TPH1R403NL1 from TOSHIBA, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Source | passive | Source terminal; pins 1, 2 and 3 are all listed as Source. |
| 2 | Source | passive | Source terminal; pins 1, 2 and 3 are all listed as Source. |
| 3 | Source | passive | Source terminal; pins 1, 2 and 3 are all listed as Source. |
| 4 | Gate | input | Gate terminal of the MOSFET, which controls the channel between Source and Drain. |
| 5 | Drain | passive | Drain terminal; pins 5, 6, 7 and 8 are all listed as Drain. |
| 6 | Drain | passive | Drain terminal; pins 5, 6, 7 and 8 are all listed as Drain. |
| 7 | Drain | passive | Drain terminal; pins 5, 6, 7 and 8 are all listed as Drain. |
| 8 | Drain | passive | Drain terminal; pins 5, 6, 7 and 8 are all listed as Drain. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-source voltage | VDSS | 30 | V | 2 | |||
| Gate-source voltage | VGSS | -20 | 20 | V | 2 | ||
| Drain current (DC) | ID | 150 | A | Tc = 25 °C (package limit, Note 2) | 2 | ||
| Drain current (DC), silicon limit | ID | 230 | A | Tc = 25 °C (silicon limit) | 2 | ||
| Drain current (pulsed) | IDP | 500 | A | t = 100 µs | 2 | ||
| Power dissipation | PD | 142 | W | Tc = 25 °C | 2 | ||
| Power dissipation | PD | 2.5 | W | Ta = 25 °C, glass-epoxy board (a), Fig. 5.1 | 2 | ||
| Power dissipation | PD | 0.8 | W | Ta = 25 °C, glass-epoxy board (b), Fig. 5.2 | 2 | ||
| Single-pulse avalanche energy | EAS | 117 | mJ | VDD = 24 V, Tch = 25 °C (initial), L = 6.3 µH, IAS = 120 A | 2 | ||
| Single-pulse avalanche current | IAS | 120 | A | VDD = 24 V, Tch = 25 °C (initial), L = 6.3 µH | 2 | ||
| Channel temperature | Tch | 150 | °C | 2 | |||
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Channel-to-case thermal resistance | Rth(ch-c) | 0.88 | °C/W | Tc = 25 °C | 2 | ||
| Channel-to-ambient thermal resistance | Rth(ch-a) | 50 | °C/W | Ta = 25 °C, glass-epoxy board (a), Note 3 | 2 | ||
| Channel-to-ambient thermal resistance | Rth(ch-a) | 156 | °C/W | Ta = 25 °C, glass-epoxy board (b), Note 4 | 2 | ||
| Gate leakage current | IGSS | -0.1 | 0.1 | µA | VGS = ±20 V, VDS = 0 V | 3 | |
| Drain cut-off current | IDSS | 10 | µA | VDS = 30 V, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage | V(BR)DSS | 30 | V | ID = 10 mA, VGS = 0 V | 3 | ||
| Drain-source breakdown voltage (VGS = -20 V) | V(BR)DSX | 15 | V | ID = 10 mA, VGS = -20 V | 3 | ||
| Gate threshold voltage | Vth | 1.3 | 2.3 | V | VDS = 10 V, ID = 0.5 mA | 3 | |
| Drain-source on-resistance | RDS(ON) | 1.7 | 2.1 | mΩ | VGS = 4.5 V, ID = 41 A | 3 | |
| Drain-source on-resistance | RDS(ON) | 1.2 | 1.4 | mΩ | VGS = 10 V, ID = 50 A | 3 | |
| Input capacitance | Ciss | 3400 | 4400 | pF | VDS = 15 V, VGS = 0 V, f = 1 MHz | 3 | |
| Reverse transfer capacitance | Crss | 93 | 200 | pF | VDS = 15 V, VGS = 0 V, f = 1 MHz | 3 | |
| Gate resistance | rg | 1.1 | 1.7 | Ω | 3 | ||
| Reverse drain current (pulsed) | IDRP | 500 | A | t = 100 µs | 3 | ||
| Diode forward voltage | VDSF | -1.2 | V | IDR = 150 A, VGS = 0 V | 3 |
CAD (KiCad official)
- Symbol:
TPH1R403NL1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tph1r403nl1-etched.step/tph1r403nl1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tph1r403nl1.step/tph1r403nl1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (8 pp, sha256
ca64c54f81fb2584, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).