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UCC28C40DR

Texas Instruments · AC-DC Controllers and Regulators · SOIC-8

UCC28C40DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COMP output Error amplifier output for loop compensation. Frequently used as the control port when a secondary-side error amplifier drives it through an opto-isolator across the isolation boundary. The amplifier is internally current-limited, so pulling COMP to GND forces zero duty cycle. High-level swing is up to VREF − 0.2V; low level is 0.1-1.1V.
2 FB input Inverting input to the error amplifier used to close the power-converter voltage-feedback loop. The noninverting reference is internally trimmed to 2.5V ±1%. Typical input bias current is 0.1µA (2µA max).
3 CS input Primary-side current-sense input and noninverting input to the PWM comparator. Connect to the current-sense resistor; the PWM uses this signal, compared against a signal proportional to COMP, to terminate the OUT switch conduction cycle-by-cycle. Maximum useful input signal is ~1V; CS-to-output delay is 35ns typical.
4 RT/CT bidirectional Fixed-frequency oscillator programming pin. Connect a timing resistor RRT from this pin to VREF and a timing capacitor CCT from this pin to GND to set the oscillator frequency (fOSC up to 1MHz). Peak-to-peak swing is ~1.9V; trimmed discharge current is 8.4mA typical at VRT/CT = 2V. For the UCC28C40, the OUT switching frequency equals fOSC.
5 GND power_in Ground return for the output driver stage and the logic/control section. All voltages in the datasheet are referenced to this pin; keep the timing-capacitor return trace to GND short and, if possible, use a separate ground trace for timing.
6 OUT output High-current totem-pole gate-drive output intended to drive an external power MOSFET directly. Sources and sinks peak currents up to ±1A with 25ns rise and 20ns fall times into 1nF. In the UCC28C40 the OUT frequency equals fOSC and can approach 100% duty cycle. OUT is actively held low when VDD is below the UVLO turn-on threshold. Absolute maximum voltage is 20V; RDS(on) ≈ 5.5Ω pull-down / 10Ω pull-up at 200mA.
7 VDD power_in Analog controller bias supply. Total VDD current is the sum of the quiescent current (~2.3mA at 52kHz) and the average OUT gate-drive current. UVLO thresholds for the UCC28C40 are 7V turn-on / 6.6V turn-off (battery-application version). Absolute maximum 20V; recommended operating maximum 18V. Requires a 0.1µF bypass cap directly to GND plus additional bulk at least 10× the driven MOSFET gate capacitance.
8 VREF power_out Trimmed 5V ±1% reference output used to bias the oscillator timing resistor and available to external loads up to 20mA. Short-circuit current is 45mA typical. Must be bypassed to GND with a ceramic cap (minimum 0.1µF) placed as close to the pin as possible, with additional bypass if driving external loads.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

  • UCC28C40DRD
  • UCC28C40DR
  • UCC28C40DRDGK
  • UCC28C40DRDGKR

CAD (KiCad official)

  • Symbol: UCC28C40DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 9fa55f996731c56b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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