component
HC32F452JEUB-QFN48TR
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), QFN-48(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHC32F452JEUB-QFN48TR
XHSC · Microcontrollers (MCU/MPU/SOC) · QFN-48(5x5)
HC32F452JEUB-QFN48TR from XHSC, in a QFN-48(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2 | bidirectional | GPIO PH2 (also EIRQ2, FCMREF, TIM4_2_CLK, SDIO2_D4, I2S3_EXCK); supports pull-up, push-pull/open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 2 | PC13 | bidirectional | GPIO PC13 (also EIRQ13, RTC_OUT, SDIO2_CK, I2S3_MCK); supports pull-up, push-pull/open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 3 | PC14/XTAL32_OUT | output | 32.768 kHz crystal oscillator output (XTAL32_OUT) that drives the external 32 kHz resonator; the pin can alternatively be used as GPIO PC14 or EIRQ14. |
| 4 | PC15/XTAL32_IN | input | 32.768 kHz crystal oscillator input (XTAL32_IN) for the external 32 kHz resonator; the pin can alternatively be used as GPIO PC15 or EIRQ15. |
| 5 | PH0/XTAL_EXT/XTAL_OUT | bidirectional | Main high-speed oscillator pin (XTAL_OUT or external clock input XTAL_EXT, 1-25 MHz external clock, 4-25 MHz crystal); also GPIO PH0 and EIRQ0, and 5 V tolerant as a digital input. |
| 6 | PH1/XTAL_IN | bidirectional | Main high-speed oscillator input (XTAL_IN) for a 4-25 MHz crystal or resonator; also GPIO PH1 and EIRQ1. |
| 7 | NRST | input | Reset pin, active low; when unused it should be connected to VCC through a pull-up resistor. |
| 8 | AVSS/VREFL | power_in | Analog ground and low ADC reference; connect to VSS (AVSS = VSS) and short to VSS when the analog modules are not used. |
| 9 | AVCC/VREFH | power_in | Analog supply, same voltage as VCC (1.8-3.6 V); the ADC reference VREFH must not exceed AVCC, and VAVCC-VREFH must stay below 1.2 V; short to AVCC when the ADC is not used. |
| 10 | PA0 | bidirectional | GPIO PA0 shared with ADC1_IN0 and CMP1_INP1; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 11 | PA1 | bidirectional | GPIO PA1 shared with ADC1_IN1 and CMP1_INP2; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 12 | PA2 | bidirectional | GPIO PA2 shared with ADC1_IN2 and CMP1_INP3; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 13 | PA3 | bidirectional | GPIO PA3 shared with ADC1_IN3, PGAVSS and CMP1_INP4; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 14 | PA4 | bidirectional | GPIO PA4 shared with ADC12_IN4, CMP2_INP1 and CMP3_INP4; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 15 | PA5 | bidirectional | GPIO PA5 shared with ADC12_IN5 and CMP2_INP2; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 16 | PA6 | bidirectional | GPIO PA6 shared with ADC12_IN6 and CMP2_INP3; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 17 | PA7 | bidirectional | GPIO PA7 shared with ADC12_IN7, CMP1_INM1, CMP2_INM1 and CMP3_INM1; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 18 | PB0 | bidirectional | GPIO PB0 shared with ADC12_IN8 and CMP3_INP1; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 19 | PB1 | bidirectional | GPIO PB1 shared with ADC12_IN9, CMP3_INP2 and wake-up input WKUP0_1; analog input voltage must not exceed VREFH/AVCC, and digital input is 5 V tolerant. |
| 20 | PB2/PVD2EXINP | bidirectional | GPIO PB2 that is also the external PVD2 comparison voltage input PVD2EXINP, WKUP0_2 and VCOUT123; digital input is 5 V tolerant. |
| 21 | PB10 | bidirectional | GPIO PB10 (also EIRQ10, ADTRG2, QSPI_QSIO2, SDIO1_D7, I2S3_EXCK); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 22 | VCAP_1 | passive | Core-voltage regulator decoupling pin; connect a capacitor of 0.1 uF or 0.22 uF (single VCAP_1 part) between this pin and VSS placed close to the pin, with ESR below 0.3 ohm. |
| 23 | VSS | power_in | Ground reference (0 V); connect to the board ground and decouple with VCC near the pin. |
| 24 | VCC | power_in | Main supply, 1.8 V to 3.6 V; decouple to VSS with the recommended capacitors placed close to the pin. |
| 25 | PB12 | bidirectional | GPIO PB12 (also EIRQ12, VCOUT1, QSPI_QSIO1, SDIO2_D1, I2S3_MCK); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 26 | PB13 | bidirectional | GPIO PB13 (also EIRQ13, VCOUT2, QSPI_QSIO0, SDIO2_D0); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 27 | PB14 | bidirectional | GPIO PB14 (also EIRQ14, VCOUT3, QSPI_QSCK, SDIO1_D6); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 28 | PB15 | bidirectional | GPIO PB15 (also EIRQ15, RTC_OUT, USART3_CK, SDIO1_CK); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 29 | PA8 | bidirectional | GPIO PA8 (also EIRQ8/WKUP2_0, MCO_1, USART1_CK, SDIO1_D1, USBFS_SOF); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 30 | PA9/USBFS_VBUS | bidirectional | GPIO PA9 that doubles as the USB FS VBUS sense input (USBFS_VBUS); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 31 | PA10/USBFS_ID | bidirectional | GPIO PA10 that doubles as the USB FS ID input (USBFS_ID); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 32 | PA11/USBFS_DM | bidirectional | USB FS D- signal of the on-chip full-speed PHY (USBFS_DM) also usable as GPIO PA11; it is not 5 V tolerant and its input voltage must stay within VCC+0.3 V with the internal pull-up/pull-down disabled above VCC+0.3 V. |
| 33 | PA12/USBFS_DP | bidirectional | USB FS D+ signal of the on-chip full-speed PHY (USBFS_DP) also usable as GPIO PA12; it is not 5 V tolerant and its input voltage must stay within VCC+0.3 V. |
| 34 | PA13/JTMS_SWDIO | bidirectional | JTAG TMS / SWD data I/O (JTMS_SWDIO) also usable as GPIO PA13; digital input is 5 V tolerant. |
| 35 | VSS | power_in | Ground reference (0 V); connect to the board ground and decouple with VCC near the pin. |
| 36 | VCC | power_in | Main supply, 1.8 V to 3.6 V; decouple to VSS with the recommended capacitors placed close to the pin. |
| 37 | PA14/JTCK_SWCLK | bidirectional | JTAG TCK / SWD clock (JTCK_SWCLK) also usable as GPIO PA14; digital input is 5 V tolerant. |
| 38 | PA15/JTDI | bidirectional | JTAG data input (JTDI) also usable as GPIO PA15; digital input is 5 V tolerant. |
| 39 | PB3/JTDO_TRACESWO | bidirectional | JTAG data output / SWO trace output (JTDO_TRACESWO) also usable as GPIO PB3; digital input is 5 V tolerant. |
| 40 | PB4/NJTRST | bidirectional | JTAG reset input (NJTRST) also usable as GPIO PB4; digital input is 5 V tolerant. |
| 41 | PB5 | bidirectional | GPIO PB5 (also EIRQ5, WKUP1_1, I2S4_EXCK, SDIO1_D3); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 42 | PB6 | bidirectional | GPIO PB6 (also EIRQ6, WKUP1_2, ADTRG2, I2S4_MCK, SDIO2_CK); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 43 | PB7 | bidirectional | GPIO PB7 (also EIRQ7, WKUP1_3, ADTRG1, SDIO1_D0); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 44 | PB11/MD | input | Mode pin MD, fixed as input; it must be held high when NRST is released, and a 4.7 kOhm pull-up to VCC is recommended; PB11 is an input-only port pin and tolerates 5 V. |
| 45 | PB8 | bidirectional | GPIO PB8 (also EIRQ8, KEYOUT7, SDIO1_D4, USBFS_DRVVBUS); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 46 | PB9 | bidirectional | GPIO PB9 (also EIRQ9, TIMA_6_TRIG, SPI2_SS1, KEYOUT6, SDIO1_D5); supports pull-up, open-drain and low/mid/high drive, and is 5 V tolerant as a digital input. |
| 47 | VSS | power_in | Ground reference (0 V); connect to the board ground and decouple with VCC near the pin. |
| 48 | VCC | power_in | Main supply, 1.8 V to 3.6 V; decouple to VSS with the recommended capacitors placed close to the pin. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | QFN-48(5x5) |
| Category | Embedded Processors & Controllers |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC | VCC | 1.8 | 3.6 | V | 12 | ||
| Operating temperature range (B grade, industrial) | -40 | 105 | ℃ | 12 | |||
| Pxy GPIO input voltage (5V tolerant, input function) | 5 | V | used as input function | 39 | |||
| PLL PFD input clock | fPLL_IN | 1 | 25 | MHz | 73 | ||
| PLL multiplier output clock | fPLL_OUT | 15 | 240 | MHz | 73 | ||
| PLL VCO output | fVCO_OUT | 240 | 480 | MHz | 73 | ||
| PLL lock time | tLOCK | 80 | 120 | µs | 73 | ||
| USB FS operating voltage VCC | VCC | 3 | 3.6 | V | 71 | ||
| USB FS input low voltage | VIL | 0.8 | V | 71 | |||
| USB FS input high voltage | VIH | 2 | V | 71 | |||
| USB FS differential input sensitivity | VDI | 0.2 | V | 71 | |||
| USB FS differential common-mode voltage | VCM | 0.8 | 2.5 | V | 71 | ||
| USB FS static output low level | VOL | 0.3 | V | RL=1.5kΩ to 3.6V | 71 | ||
| USB FS static output high level | VOH | 2.8 | 3.6 | V | RL=15kΩ to VSS | 71 | |
| USB FS cross-over voltage | VCRS | 1.3 | 2 | V | CL=50pF | 71 | |
| USB FS rise time | tR | 4 | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 71 | |
| USB FS fall time | tF | 4 | 20 | ns | CL=50pF, 10%~90% of /VOH-VOL/ | 71 | |
| USB FS rise/fall time ratio | tRFMA | 90 | 111.1 | % | CL=50pF | 71 | |
| USB FS pull-up resistance (idle state) | RPU | 0.9 | 1.2 | 1.575 | kΩ | VIN= VSS, idle state | 71 |
| USB FS pull-up resistance (device mode) | RPU | 1.425 | 2.3 | 3.09 | kΩ | VIN= VSS, in device mode | 71 |
| I2C SCL clock frequency | fSCL | 0 | 100 | KHz | Standard mode (SM) | 68 | |
| I2C SCL clock frequency | fSCL | 0 | 400 | KHz | Fast mode (FM) | 68 | |
| I2C START/repeated START hold time | tHD;STA | 4 | us | Standard mode (SM) | 68 | ||
| I2C START/repeated START hold time | tHD;STA | 0.6 | us | Fast mode (FM) | 68 | ||
| I2C SCL low period | tLOW | 4.7 | us | Standard mode (SM) | 68 | ||
| I2C SCL low period | tLOW | 1.3 | us | Fast mode (FM) | 68 | ||
| I2C SCL high period | tHIGH | 4 | us | Standard mode (SM) | 68 | ||
| I2C SCL high period | tHIGH | 0.6 | us | Fast mode (FM) | 68 | ||
| I2C repeated START setup time | tSU;STA | 4.7 | us | Standard mode (SM) | 68 | ||
| I2C repeated START setup time | tSU;STA | 0.6 | us | Fast mode (FM) | 68 | ||
| I2C data hold time | tHD;DAT | 0 | us | Standard mode (SM) | 68 | ||
| I2C SCL/SDA rise time | tR | 1000 | ns | Standard mode (SM) | 68 | ||
| I2C SCL/SDA rise time | tR | 6.5 | 300 | ns | Fast mode (FM) | 68 | |
| I2C SCL/SDA fall time | tF | 300 | ns | Standard mode (SM) | 68 | ||
| I2C SCL/SDA fall time | tF | 6.5 | 300 | ns | Fast mode (FM) | 68 | |
| I2C STOP setup time | tSU;STO | 4 | us | Standard mode (SM) | 68 | ||
| I2C STOP setup time | tSU;STO | 0.6 | us | Fast mode (FM) | 68 | ||
| I2C bus free time between STOP and START | tBUF | 4.7 | us | Standard mode (SM) | 68 | ||
| I2C bus free time between STOP and START | tBUF | 1.3 | us | Fast mode (FM) | 68 | ||
| I2C load capacitance | Cb | 400 | pF | Standard mode (SM) | 68 | ||
| SPI SCK clock rise and fall time (Master) | tsckr/tsckf | 5 | ns | 69 | |||
| SPI SCK clock rise and fall time (Slave) | tsckr/tsckf | 1 | us | 69 | |||
| SPI data input setup time (Master) | tsu | 4 | ns | 69 | |||
| SPI data input setup time (Slave) | tsu | 5 | ns | C=30pF | 69 | ||
| SPI data input hold time (Slave) | th | 20 | ns | 69 | |||
| SPI data output delay (Master) | tod | 8 | ns | 69 | |||
| SPI data output delay (Slave) | tod | 20 | ns | 69 | |||
| SPI data output hold time (Master) | toh | 0 | ns | 69 | |||
| SPI data output hold time (Slave) | toh | 0 | ns | 69 | |||
| SPI MOSI/MISO rise and fall time (Master) | tdr/tdf | 5 | ns | 69 | |||
| SPI MOSI/MISO rise and fall time (Slave) | tdr/tdf | 1 | us | 69 | |||
| SPI SS rise and fall time (Master) | tssr/tssf | 5 | ns | 69 | |||
| SPI SS rise and fall time (Slave) | tssr/tssf | 1 | us | 69 | |||
| SPI SCK clock cycle (Slave) | tpcyc | 6 | 4096 | tpcyc | 69 | ||
| USART CSI input clock width | tCKw | 0.4 | 0.6 | tScyc | 65 | ||
| USART CSI transmit delay | tTD | 28 | ns | CSI | 65 | ||
| USART CSI receive data setup time | tRDS | 15 | ns | CSI | 65 | ||
| USART CSI receive data hold time | tRDH | 5 | ns | CSI | 65 |
CAD (KiCad official)
- Symbol:
HC32F452JEUB-QFN48TR - Footprint:
Package_DFN_QFN:QFN-48-1EP_5x5mm_P0.35mm_EP3.7x3.7mm - 3D model: QFN-48(5x5) (KiCad packages3D, STEP)
- 3D model files:
hc32f452jeub-qfn48tr-etched.step/hc32f452jeub-qfn48tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f452jeub-qfn48tr.step/hc32f452jeub-qfn48tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (97 pp, sha256
66fdc58cad687d2f, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).