EG8405 from EG Micro, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUTL+	output	Left channel non-inverting Class-D speaker output. Connects directly to one terminal of the left speaker (filterless drive).
2	PGND	power_in	Power ground return for the H-bridge output stage. Tie to system ground plane with low-impedance connection.
3	OUTL-	output	Left channel inverting Class-D speaker output. Connects directly to the other terminal of the left speaker (filterless BTL drive).
4	PVDD	power_in	Power supply for the H-bridge output stage, 2.5V to 5.7V (absolute max 6.0V). Bypass with 1µF and bulk 1000µF close to the pin.
5	MUTE	input	Active-low mute control input. Drive low to mute the outputs; drive high for normal operation.
6	VDD	power_in	Analog supply, 2.5V to 5.7V (typical 5.0V, absolute max 6.0V). UVLO rising threshold typ 2.4V, falling 2.2V. Bypass with 1µF and 0.1µF close to the pin.
7	INL	input	Left channel analog audio input. AC-coupled via input capacitor (typ 0.1µF) to set the high-pass corner with the internal input resistance.
8	VREF	passive	Internal bias/reference (VDD/2) decoupling pin. Connect a 1µF capacitor to ground; do not drive externally.
9	NCN	input	Anti-clipping (No-Clipping-Noise) function pin. Tie logic H or L for NCN-OFF mode, or connect external Rex/Cex to configure attack/release time and THD vs output power (e.g. Rex=20kΩ, Cex=1µF → THD+N=10%, PO=3.2W at 4Ω). Max attenuation typ -10dB.
10	INR	input	Right channel analog audio input. AC-coupled via input capacitor (typ 0.1µF) to set the high-pass corner with the internal input resistance.
11	GND	power_in	Analog ground reference for the small-signal, bias, and control blocks. Tie to system ground plane.
12	SHDN	input	Active-low system shutdown control. VIH ≥ 1.35V for normal operation; VIL ≤ 0.1V forces shutdown (typ IPD = 1µA at Ta=25°C).
13	PVDD	power_in	Power supply for the H-bridge output stage (paralleled with pin 4), 2.5V to 5.7V. Bypass with 1µF close to the pin.
14	OUTR-	output	Right channel inverting Class-D speaker output. Connects directly to one terminal of the right speaker (filterless BTL drive).
15	PGND	power_in	Power ground return for the H-bridge output stage (paralleled with pin 2). Tie to system ground plane with low-impedance connection.
16	OUTR+	output	Right channel non-inverting Class-D speaker output. Connects directly to the other terminal of the right speaker (filterless BTL drive).

Key specifications

Parameter	Value
Manufacturer	EG Micro
Package	SOP-16
Category	Op-amp/Cmp
Pins	16

CAD (KiCad official)

Symbol: EG8405
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`eg8405.step`	217 KB	You want the bare part, or you mark your own boards.
`eg8405-etched.step`	2.1 MB	You want the part with `EG8405` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 512 faces against 267 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: EG Micro datasheet (4 pp, sha256 96c51e48903e8233, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF