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TMS320F28035PAGT

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Texas Instruments Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerstms320f28035pagtfactory-2.0.0extractor-text
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Contents

README

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TMS320F28035PAGT

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)

TMS320F28035PAGT from Texas Instruments, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GPIO22/EQEP1S/LINTXA bidirectional Multiplexed pin: general-purpose I/O GPIO22, or eQEP1 strobe input (EQEP1S), or LIN transmit (LINTXA), as selected by GPIO mux.
2 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO bidirectional Multiplexed pin: GPIO32, or I2C data (SDAA), or ePWM external sync input (EPWMSYNCI), or ADC start-of-conversion A output (ADCSOCAO).
3 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO bidirectional Multiplexed pin: GPIO33, or I2C clock (SCLA), or ePWM sync output (EPWMSYNCO), or ADC start-of-conversion B output (ADCSOCBO).
4 GPIO23/EQEP1I/LINRXA bidirectional Multiplexed pin: GPIO23, or eQEP1 index input (EQEP1I), or LIN receive (LINRXA).
5 VDD power_in Digital core logic supply voltage input.
6 VSS power_in Digital core logic ground return.
7 XRS bidirectional Active-low external device reset; can be driven externally to reset the device and is driven low by the device during an internal reset condition.
8 TRST input Active-low JTAG test reset input used to place the JTAG TAP controller into reset/normal operating state.
9 ADCINA7 input Analog input channel A7 to the on-chip 12-bit ADC.
10 ADCINA6/COMP3A/AIO6 input Multiplexed analog pin: ADC channel A6 input, comparator 3 A-input (COMP3A), or analog I/O AIO6.
11 ADCINA4/COMP2A/AIO4 input Multiplexed analog pin: ADC channel A4 input, comparator 2 A-input (COMP2A), or analog I/O AIO4.
12 ADCINA3 input Analog input channel A3 to the on-chip 12-bit ADC.
13 ADCINA2/COMP1A/AIO2 input Multiplexed analog pin: ADC channel A2 input, comparator 1 A-input (COMP1A), or analog I/O AIO2.
14 ADCINA1 input Analog input channel A1 to the on-chip 12-bit ADC.
15 ADCINA0/VREFHI input Shared pin: ADC channel A0 input or the high analog voltage reference (VREFHI); these two functions share the same physical pin and cannot be used simultaneously (datasheet note A, Fig 5-2).
16 VDDA power_in Analog supply voltage input for the ADC and analog comparator circuitry.
17 VSSA/VREFLO power_in Analog ground; on this 64-pin PAG package VREFLO is always internally tied to VSSA at this pin (datasheet note B, Fig 5-2).
18 ADCINB0 input Analog input channel B0 to the on-chip 12-bit ADC.
19 ADCINB1 input Analog input channel B1 to the on-chip 12-bit ADC.
20 ADCINB2/COMP1B/AIO10 input Multiplexed analog pin: ADC channel B2 input, comparator 1 B-input (COMP1B), or analog I/O AIO10.
21 ADCINB3 input Analog input channel B3 to the on-chip 12-bit ADC.
22 ADCINB4/COMP2B/AIO12 input Multiplexed analog pin: ADC channel B4 input, comparator 2 B-input (COMP2B), or analog I/O AIO12.
23 ADCINB6/COMP3B/AIO14 input Multiplexed analog pin: ADC channel B6 input, comparator 3 B-input (COMP3B), or analog I/O AIO14.
24 ADCINB7 input Analog input channel B7 to the on-chip 12-bit ADC.
25 GPIO31/CANTXA bidirectional Multiplexed pin: GPIO31 or eCAN-A transmit (CANTXA).
26 GPIO30/CANRXA bidirectional Multiplexed pin: GPIO30 or eCAN-A receive (CANRXA).
27 GPIO29/SCITXDA/SCLA/TZ3 bidirectional Multiplexed pin: GPIO29, SCI-A transmit (SCITXDA), I2C clock (SCLA), or ePWM trip-zone input TZ3 (active low).
28 VSS power_in Digital core logic ground return.
29 VDDIO power_in Digital I/O buffer supply voltage input.
30 TEST2 unconnected Reserved factory test pin shown on the package pin diagram; not assigned any user function in the provided text.
31 GPIO9/EPWM5B/LINTXA/HRCAP1 bidirectional Multiplexed pin: GPIO9, ePWM5 output B (EPWM5B), LIN transmit (LINTXA), or high-resolution capture input 1 (HRCAP1).
32 GPIO28/SCIRXDA/SDAA/TZ2 bidirectional Multiplexed pin: GPIO28, SCI-A receive (SCIRXDA), I2C data (SDAA), or ePWM trip-zone input TZ2 (active low).
33 GPIO18/SPICLKA/LINTXA/XCLKOUT bidirectional Multiplexed pin: GPIO18, SPI-A clock (SPICLKA), LIN transmit (LINTXA), or external clock output (XCLKOUT).
34 GPIO17/SPISOMIA/TZ3 bidirectional Multiplexed pin: GPIO17, SPI-A slave-out/master-in (SPISOMIA), or ePWM trip-zone input TZ3 (active low).
35 GPIO8/EPWM5A/ADCSOCAO bidirectional Multiplexed pin: GPIO8, ePWM5 output A (EPWM5A), or ADC start-of-conversion A output (ADCSOCAO).
36 GPIO16/SPISIMOA/TZ2 bidirectional Multiplexed pin: GPIO16, SPI-A slave-in/master-out (SPISIMOA), or ePWM trip-zone input TZ2 (active low).
37 GPIO12/TZ1/SCITXDA bidirectional Multiplexed pin: GPIO12, ePWM trip-zone input TZ1 (active low), or SCI-A transmit (SCITXDA).
38 GPIO7/EPWM4B/SCIRXDA bidirectional Multiplexed pin: GPIO7, ePWM4 output B (EPWM4B), or SCI-A receive (SCIRXDA).
39 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO bidirectional Multiplexed pin: GPIO6, ePWM4 output A (EPWM4A), ePWM external sync input (EPWMSYNCI), or ePWM sync output (EPWMSYNCO).
40 X2 passive On-chip crystal oscillator output terminal for connection to an external crystal/resonator.
41 X1 passive On-chip crystal oscillator input terminal for connection to an external crystal/resonator.
42 VSS power_in Digital core logic ground return.
43 VDD power_in Digital core logic supply voltage input.
44 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 bidirectional Multiplexed pin: GPIO19, external clock input (XCLKIN), SPI-A slave transmit enable (SPISTEA, active low), LIN receive (LINRXA), or enhanced capture input 1 (ECAP1).
45 GPIO38/TCK/XCLKIN bidirectional Multiplexed pin: GPIO38, JTAG test clock (TCK), or external clock input (XCLKIN).
46 GPIO37/TDO bidirectional Multiplexed pin: GPIO37 or JTAG test data output (TDO).
47 GPIO35/TDI bidirectional Multiplexed pin: GPIO35 or JTAG test data input (TDI).
48 GPIO36/TMS bidirectional Multiplexed pin: GPIO36 or JTAG test mode select (TMS).
49 GPIO11/EPWM6B/LINRXA/HRCAP2 bidirectional Multiplexed pin: GPIO11, ePWM6 output B (EPWM6B), LIN receive (LINRXA), or high-resolution capture input 2 (HRCAP2).
50 GPIO5/EPWM3B/SPISIMOA/ECAP1 bidirectional Multiplexed pin: GPIO5, ePWM3 output B (EPWM3B), SPI-A slave-in/master-out (SPISIMOA), or enhanced capture input 1 (ECAP1).
51 GPIO4/EPWM3A bidirectional Multiplexed pin: GPIO4 or ePWM3 output A (EPWM3A).
52 GPIO10/EPWM6A/ADCSOCBO bidirectional Multiplexed pin: GPIO10, ePWM6 output A (EPWM6A), or ADC start-of-conversion B output (ADCSOCBO).
53 GPIO3/EPWM2B/SPISOMIA/COMP2OUT bidirectional Multiplexed pin: GPIO3, ePWM2 output B (EPWM2B), SPI-A slave-out/master-in (SPISOMIA), or comparator 2 digital output (COMP2OUT).
54 GPIO2/EPWM2A bidirectional Multiplexed pin: GPIO2 or ePWM2 output A (EPWM2A).
55 GPIO1/EPWM1B/COMP1OUT bidirectional Multiplexed pin: GPIO1, ePWM1 output B (EPWM1B), or comparator 1 digital output (COMP1OUT).
56 GPIO0/EPWM1A bidirectional Multiplexed pin: GPIO0 or ePWM1 output A (EPWM1A).
57 VDDIO power_in Digital I/O buffer supply voltage input.
58 VSS power_in Digital core logic ground return.
59 VDD power_in Digital core logic supply voltage input.
60 VREGENZ input Active-low internal voltage regulator enable/disable control input; pulled to the appropriate level to select whether the on-chip VREG is used.
61 GPIO34/COMP2OUT/COMP3OUT bidirectional Multiplexed pin: GPIO34, comparator 2 digital output (COMP2OUT), or comparator 3 digital output (COMP3OUT).
62 GPIO20/EQEP1A/COMP1OUT bidirectional Multiplexed pin: GPIO20, eQEP1 quadrature input A (EQEP1A), or comparator 1 digital output (COMP1OUT).
63 GPIO21/EQEP1B/COMP2OUT bidirectional Multiplexed pin: GPIO21, eQEP1 quadrature input B (EQEP1B), or comparator 2 digital output (COMP2OUT).
64 GPIO24/ECAP1 bidirectional Multiplexed pin: GPIO24 or enhanced capture input 1 (ECAP1).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: TMS320F28035PAGT
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: tms320f28035pagt-etched.step / tms320f28035pagt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms320f28035pagt.step / tms320f28035pagt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (176 pp, sha256 cb9ccecfd6b5c484, retrieved 2026-09-29, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF