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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LM5127QRGZRQ1

Texas Instruments · DC-DC Converters · VQFN-48-EP(7x7)

LM5127QRGZRQ1 from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SLEEP1/BMIN_PRG	input	In boost mode, SLEEP1 above 1.0 V allows the channel to enter sleep mode; in buck mode it is the programmable battery-monitor threshold input (grounded if unused).
2	SS1	bidirectional	CH1 soft-start programming pin, where the soft-start capacitor sets the ramp time from a 20 µA charge current and pulling SS to ground stops switching.
3	FB1/VOSEL1	input	CH1 error-amplifier feedback or fixed-output select; in buck, tie to AGND for 3.3 V or VDD for 5 V, and in boost always use a feedback resistor divider (0.8 V reference, VOUT up to 42 V).
4	COMP1	output	CH1 internal transconductance error-amplifier output, with loop compensation components connected between this pin and AGND.
5	CSB1/VOUT1	input	CH1 current-sense amplifier input that is the positive input in boost and the negative input in buck, and also senses the fixed output voltage in buck fixed-output options.
6	CSA1	input	CH1 current-sense amplifier input that is the negative input in boost and the positive input in buck.
7	SENSE1/BMIN_FIX	input	In boost mode this pin senses the output voltage and should be placed near the high-side MOSFET drain; in buck mode it is the fixed-threshold battery-monitor input (5.7 V falling, 6.0 V rising).
8	HB1	power_in	CH1 high-side gate-driver bootstrap supply, with a 0.1 µF capacitor between HB1 and SW1 and an external bootstrap diode from VCC in buck configuration.
9	SW1	passive	CH1 switch node connected through a short low-inductance path directly to the high-side MOSFET source and low-side MOSFET drain.
10	HO1	output	CH1 high-side gate-driver output, connected through a short low-inductance path to the N-channel MOSFET gate.
11	PGND1	power_in	CH1 power ground, connected through a short low-inductance path directly to the low-side MOSFET source.
12	LO1	output	CH1 low-side gate-driver output, connected through a short low-inductance path directly to the N-channel MOSFET gate.
13	SS2	bidirectional	CH2 soft-start programming pin, where the soft-start capacitor sets the ramp time and pulling SS to ground stops switching.
14	FB2/VOSEL2	input	CH2 feedback or fixed-output select pin, rated 0 to 5.25 V, that programs the common output voltage when CH2 and CH3 operate as dual-phase buck.
15	COMP2	output	CH2 internal transconductance error-amplifier output, with loop compensation components connected between this pin and AGND.
16	CSB2/VOUT2	input	CH2 current-sense amplifier negative input in buck, which also senses the fixed output voltage option.
17	CSA2	input	CH2 current-sense amplifier input (positive input in buck).
18	VCCX	power_in	Optional external VCC supply input, which must be between 4.5 V and 5.25 V and connects internally to VCC when above 4.5 V; use a 0.47 µF capacitor to PGND, or tie to PGND if unused.
19	VCC	power_in	Auxiliary supply pin for the internal regulator, requiring a 10 µF VCC capacitor to power ground (recommended minimum 10 µF).
20	HB2	power_in	CH2 high-side gate-driver bootstrap supply, with a 0.1 µF capacitor between HB2 and SW2.
21	SW2	passive	CH2 switch node connected through a short low-inductance path to the high-side MOSFET source and low-side MOSFET drain.
22	HO2	output	CH2 high-side gate-driver output, connected through a short low-inductance path to the N-channel MOSFET gate.
23	PGND2	power_in	CH2 power ground, connected through a short low-inductance path directly to the low-side MOSFET source.
24	LO2	output	CH2 low-side gate-driver output, connected through a short low-inductance path directly to the N-channel MOSFET gate.
25	LO3	output	CH3 low-side gate-driver output, connected through a short low-inductance path directly to the N-channel MOSFET gate.
26	PGND3	power_in	CH3 power ground, connected through a short low-inductance path directly to the low-side MOSFET source.
27	HO3	output	CH3 high-side gate-driver output, connected through a short low-inductance path to the N-channel MOSFET gate.
28	SW3	passive	CH3 switch node connected through a short low-inductance path to the high-side MOSFET source and low-side MOSFET drain.
29	HB3	power_in	CH3 high-side gate-driver bootstrap supply, with a 0.1 µF capacitor between HB3 and SW3.
30	BIAS	power_in	Input to the VCC regulator, accepting 3.8 V to 42 V (absolute maximum 50 V), with a 1 µF local capacitor between BIAS and ground.
31	CFG/MODE	input	Device configuration (boost or buck, single or dual phase) and light-load mode select pin, programmed by a resistor from CFG to AGND during initial configuration; 57.6 kΩ from SS to AGND enables diode emulation in FPWM mode.
32	CSA3	input	CH3 current-sense amplifier input (positive input in buck).
33	CSB3/VOUT3/VDDX	input	CH3 current-sense negative input that senses the fixed VOUT3 option; as VDDX it is an optional VDD supply input connected internally to VDD when below 3.4 V in deep-sleep with 3.3 V VOUT3.
34	COMP3	output	CH3 internal transconductance error-amplifier output, with loop compensation between this pin and AGND; left floating in dual-phase configuration.
35	FB3/VOSEL3	input	CH3 feedback or fixed-output select pin, rated 0 to 5.25 V, that must be tied to ground in dual-phase buck configuration.
36	SS3	bidirectional	CH3 soft-start programming pin, which is not used (left floating) in dual-phase buck configuration.
37	VDD	power_in	Auxiliary supply pin for VDD, requiring a 0.1 µF capacitor to AGND, with VDD above 3.1 V starting the initial device configuration.
38	RT	bidirectional	Switching-frequency programming pin, where a single resistor from RT to AGND sets the frequency (RT regulated to 0.5 V) over 100 kHz to 2.2 MHz when no external SYNC clock is applied.
39	AGND	power_in	Analog ground pin, connected through a wide and short path to the analog ground plane.
40	RES	output	Restart-timer pin, where a capacitor from RES to AGND sets the hiccup off-time, AGND connection latches off after a fault, and VDD connection disables hiccup mode during initial power-up.
41	SYNC/DITHER/VCC_HOLD	bidirectional	External sync clock input (200 kHz to 2.2 MHz), dither-capacitor pin for ±7% spread-spectrum, or VCC_HOLD input where above 2.0 V keeps VCC active when all EN pins are low; tie to AGND if unused.
42	EN3	input	CH3 enable pin, where the channel is off below 0.4 V and must be pulled above 2.0 V to enable; connect to BIAS if not user-controlled.
43	EN2	input	CH2 enable pin, where the channel is off below 0.4 V and must be pulled above 2.0 V to enable; in dual-phase configuration it is the master enable for CH2 and CH3.
44	EN1	input	CH1 enable pin, where the channel is off below 0.4 V and must be pulled above 2.0 V to enable; connect to BIAS if not user-controlled.
45	PGOOD3	output	CH3 power-good indicator with open-drain output, which is disabled in dual-phase buck configuration.
46	PGOOD2	output	CH2 power-good indicator with open-drain output that is pulled low when the output is outside its regulation window in buck or below target in boost.
47	PGOOD1	output	CH1 power-good indicator with open-drain output that is pulled low when VOUT is outside its regulation window in buck or below target in boost.
48	DIS/BMOUT	output	In boost, the divider-disconnect output pulled low when any channel is active; in buck, the battery-monitor output pulled to AGND when BMIN_FIX is below 5.7 V or BMIN_PRG is below 1.0 V.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(7x7)
Category	Power Management (PMIC)
Pins	49

CAD (KiCad official)

Symbol: LM5127QRGZRQ1
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: lm5127qrgzrq1-etched.step / lm5127qrgzrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5127qrgzrq1.step / lm5127qrgzrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (59 pp, sha256 020db9065355f5a0, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF