component
ncp1380ddr2g
Public Made by Adomby adom
onsemi AC-DC Controllers and Regulators, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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README
markdownNCP1380DDR2G
onsemi · AC-DC Controllers and Regulators · SOIC-8
NCP1380DDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ZCD | input | Zero Crossing Detection input - connected to the transformer auxiliary winding to detect core-reset events (55 mV typ. falling threshold, 35 mV hysteresis). Also serves as the Over Power Protection (OPP) input: a negative voltage down to -300 mV applied during on-time reduces the internal peak-current setpoint by up to 37.5%. Internally clamped (-0.7 V low / +10 V high), ±3/-2 mA max. |
| 2 | FB | input | Feedback input from optocoupler collector for output regulation. Internally pulled up (~18 kΩ) to VDD. FB voltage sets the operating valley (1st→4th) and enters VCO frequency-foldback mode below 0.8 V (falling)/1.4 V (rising). Peak-current setpoint = VFB/4. |
| 3 | CS | input | Current Sense input monitoring the primary MOSFET peak current via an external sense resistor. Cycle-by-cycle current limit at VILIM = 0.8 V (with 275 ns leading-edge blanking). A second faster comparator at VCS(stop) = 1.2 V (120 ns LEB) provides immediate winding-short protection. |
| 4 | GND | power_in | Controller ground reference for all internal circuitry and the gate driver return. |
| 5 | DRV | output | Gate-driver output to the external primary MOSFET. +500 mA source / -800 mA sink peak capability (RSRC ≈ 20 Ω, RSNK ≈ 12.5 Ω). Output high clamped to ~13 V typ (10.5-15.5 V), rise/fall ≈ 40/25 ns into 1 nF. Absolute max 20 V, ±1000 mA. |
| 6 | VCC | power_in | Controller supply, fed from an auxiliary winding. VCC(on) = 17 V typ startup, VCC(off) = 9 V typ UVLO, operating up to 28 V max. Startup current ~10 µA; ICC ≈ 2.65 mA switching at 65 kHz with 1 nF DRV load. Clamped to VCC(latch) ≈ 7.2 V when latched off. |
| 7 | Fault | bidirectional | Combined protection pin. On the D variant (this part): Brown-Out / OVP - a resistor divider from the HV bulk rail is sensed against VBO = 0.8 V (falling) with a 10 µA hysteresis source; a zener-diode injection above VOVP = 2.5 V latches the controller off. Internal clamp Rclamp ≈ 1.55 kΩ / Vclamp ≈ 1.2 V limits pin voltage; open-pin clamp 1.0-1.4 V. |
| 8 | CT | passive | Timing-capacitor pin for VCO/frequency-foldback mode. An external capacitor (≈220 pF recommended) is charged by a 20 µA source and compared to an FB-derived threshold; when it reaches the threshold the cap is discharged and a new switching period starts. VCT(MAX) ≈ 5.4 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
NCP1380DDR2GADR2GNCP1380DDR2GBDR2GNCP1380DDR2GCDR2GNCP1380DDR2G
CAD (KiCad official)
- Symbol:
NCP1380DDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncp1380ddr2g-etched.step/ncp1380ddr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp1380ddr2g.step/ncp1380ddr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (None pp, sha256
8261db6e470f022e, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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