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SN65LVDS391DR

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDS391DR

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDS391DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN1,2 input Enable input for channels 1 and 2; active-high logic drives Y and Z outputs, low logic forces outputs to high-impedance.
2 1A input LVTTL input signal for channel 1; accepts 0.8 V (low) to 2.0 V (high) logic levels.
3 2A input LVTTL input signal for channel 2; accepts 0.8 V (low) to 2.0 V (high) logic levels.
4 VCC power_in Supply voltage; operates from 3.0 V to 3.6 V with nominal 3.3 V operation.
5 GND power_in Ground reference pin.
6 3A input LVTTL input signal for channel 3; accepts 0.8 V (low) to 2.0 V (high) logic levels.
7 4A input LVTTL input signal for channel 4; accepts 0.8 V (low) to 2.0 V (high) logic levels.
8 EN3,4 input Enable input for channels 3 and 4; active-high logic drives Y and Z outputs, low logic forces outputs to high-impedance.
9 4Z output Differential LVDS inverting output for channel 4; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
10 4Y output Differential LVDS non-inverting output for channel 4; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
11 3Z output Differential LVDS inverting output for channel 3; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
12 3Y output Differential LVDS non-inverting output for channel 3; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
13 2Z output Differential LVDS inverting output for channel 2; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
14 2Y output Differential LVDS non-inverting output for channel 2; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
15 1Z output Differential LVDS inverting output for channel 1; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.
16 1Y output Differential LVDS non-inverting output for channel 1; produces 247 to 454 mV differential magnitude into 100 Ω load when enabled.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDS391DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvds391dr-etched.step / sn65lvds391dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds391dr.step / sn65lvds391dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 0f1613a3d18c924d, retrieved 2026-09-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF