component
HC32F448KCTI-LQFP64
Public Made by Adomby adom
XHSC Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownHC32F448KCTI-LQFP64
XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
HC32F448KCTI-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PH2/FG2 | bidirectional | GPIO, 5V-tolerant (input must not exceed 5 V); alternate functions include EIRQ2, TRACED2 and FCMREF (frequency-monitor reference clock input). |
| 2 | PC13/FG2 | bidirectional | GPIO, 5V-tolerant (input must not exceed 5 V); alternate functions include EIRQ13, RTC_OUT and VCOUT4. |
| 3 | PC14/XTAL32_IN | input | External 32.768 kHz (sub-clock) oscillator input; the pin is also usable as a 5V-tolerant GPIO (PC14). |
| 4 | PC15/XTAL32_OUT | output | External 32.768 kHz (sub-clock) oscillator output; the pin is also usable as a 5V-tolerant GPIO (PC15). |
| 5 | PH0/XTAL_IN | input | External main clock oscillator input for a 4-25 MHz crystal or resonator; the pin is also usable as a 5V-tolerant GPIO (PH0). |
| 6 | PH1/XTAL_EXT/XTAL_OUT | bidirectional | External main clock input (1-25 MHz external clock source) or main oscillator output (XTAL_OUT); the pin is also usable as a 5V-tolerant GPIO (PH1). |
| 7 | NRST | input | Reset input, active low; when not used, connect a resistor to VCC as a pull-up. |
| 8 | PC0/ADC12_IN10/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC12_IN10 and comparator inputs CMP3_INP3/CMP4_INP3. |
| 9 | PC1/ADC12_IN11/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC12_IN11 analog input. |
| 10 | PC2/ADC1_IN12/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC1_IN12 analog input. |
| 11 | PC3/ADC1_IN13/FG1 | bidirectional | GPIO not 5V-tolerant (input must not exceed VCC); analog input must not exceed VREFH/AVCC; ADC1_IN13 and comparator input CMP1_INM2. |
| 12 | AVSS/VREFL | power_in | Analog ground and low-side ADC reference; tie to VSS when no separate analog supply is used and do not leave floating. |
| 13 | AVCC/VREFH | power_in | Analog supply at the same voltage as VCC (1.8-3.6 V) and high-side ADC reference; tie to VCC when no separate analog supply is used and do not leave floating. |
| 14 | PA0/ADC1_IN0/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC1_IN0 and CMP1_INP1 analog inputs. |
| 15 | PA1/ADC1_IN1/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC1_IN1 and CMP1_INP2 analog inputs. |
| 16 | PA2/ADC1_IN2/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC1_IN2 and CMP1_INP3 analog inputs. |
| 17 | PA3/ADC1_IN3/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC1_IN3, CMP1_INP4 and CMP2_INP4 analog inputs. |
| 18 | VSS | power_in | Power ground, 0 V; decouple VCC to this pin with capacitors placed close to the pins. |
| 19 | VCC | power_in | Power supply, 1.8 V to 3.6 V; place decoupling capacitors close to the VSS pin. |
| 20 | PA4/ADC12_IN4/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC12_IN4, CMP2_INP1, CMP3_INP4 and DAC_OUT1 analog signals. |
| 21 | PA5/ADC12_IN5/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC12_IN5, CMP2_INP2 and DAC_OUT2 analog signals. |
| 22 | PA6/ADC123_IN6/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC123_IN6 and CMP2_INP3 analog inputs. |
| 23 | PA7/ADC123_IN7/FG1 | bidirectional | GPIO not 5V-tolerant (input must not exceed VCC); analog input must not exceed VREFH/AVCC; ADC123_IN7 and CMP1234_INM1 analog inputs. |
| 24 | PC4/ADC1_IN14/FG1 | bidirectional | GPIO not 5V-tolerant (input must not exceed VCC); analog input must not exceed VREFH/AVCC; ADC1_IN14 and CMP2_INM2 analog inputs. |
| 25 | PC5/ADC1_IN15/FG1 | bidirectional | GPIO not 5V-tolerant (input must not exceed VCC); analog input must not exceed VREFH/AVCC; ADC1_IN15 and CMP3_INM2 analog inputs. |
| 26 | PB0/ADC123_IN8/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC123_IN8 and CMP3_INP1 analog inputs. |
| 27 | PB1/ADC123_IN9/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC123_IN9 and CMP4_INP2 analog inputs. |
| 28 | PB2/PVD2EXINP/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); also the PVD2 external comparison voltage input PVD2EXINP. |
| 29 | PB10/ADC3_IN11/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); analog input must not exceed VREFH/AVCC; ADC3_IN11 analog input. |
| 30 | VCAP_1 | passive | Core voltage pin; connect a capacitor close to VSS to stabilize the core voltage as specified in the electrical characteristics. |
| 31 | VSS | power_in | Power ground, 0 V. |
| 32 | VCC | power_in | Power supply, 1.8 V to 3.6 V; place decoupling capacitors close to the VSS pin. |
| 33 | PB12/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ12, VCOUT1 and QSPI_IO1. |
| 34 | PB13/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ13, VCOUT2 and QSPI_IO0. |
| 35 | PB14/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ14, VCOUT3 and QSPI_SCK. |
| 36 | PB15/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ15, RTC_OUT and USART3_CK. |
| 37 | PC6/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ6, CTCREF and QSPI_SCK. |
| 38 | PC7/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ7, TMR4_2_CLK and QSPI_NSS. |
| 39 | PC8/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ8, USART3_CK and EXMC_DATA14. |
| 40 | PC9/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ9, MCO_2 and EXMC_DATA15. |
| 41 | PA8/FG1 | bidirectional | GPIO not 5V-tolerant (input must not exceed VCC); also comparator input CMP4_INM2 and MCO_1 clock output. |
| 42 | PA9/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); also comparator input CMP4_INP1 and CTCREF. |
| 43 | PA10/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); also comparator input CMP4_INP4 and USART6_CK. |
| 44 | PA11/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ11, EMB_IN1 and USART5_CK. |
| 45 | PA12/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ12, USART6_CK and EXMC_DATA6. |
| 46 | PA13/JTMS_SWDIO/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); serves as JTAG TMS / SWD data I/O (JTMS_SWDIO) in debug mode. |
| 47 | VSS | power_in | Power ground, 0 V. |
| 48 | VCC | power_in | Power supply, 1.8 V to 3.6 V; place decoupling capacitors close to the VSS pin. |
| 49 | PA14/JTCK_SWCLK/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); serves as JTAG TCK / SWD clock (JTCK_SWCLK) in debug mode. |
| 50 | PA15/JTDI/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); serves as JTAG data input (JTDI) in debug mode. |
| 51 | PC10/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ10, TMR4_3_OUH and TMRA_5_PWM1. |
| 52 | PC11/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ11, TMR4_3_OVH and TMRA_5_PWM2. |
| 53 | PC12/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ12, TMR4_3_OWH and TMRA_5_PWM3. |
| 54 | PD2/FG1 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ2, TMR4_1_OXH and TMRA_2_PWM4. |
| 55 | PB3/JTDO_SWO/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); serves as JTAG TDO / SWO trace output (JTDO_TRACESWO) in debug mode. |
| 56 | PB4/JTRST/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); serves as JTAG reset input (NJTRST) in debug mode. |
| 57 | PB5/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ5, WKUP1_1 and ADTRG3. |
| 58 | PB6/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ6, WKUP1_2 and ADTRG2. |
| 59 | PB7/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ7, WKUP1_3 and ADTRG1. |
| 60 | PB11/MD | bidirectional | Mode input MD: must be held low when NRST is released, with a recommended 4.7 kΩ pull-down to VSS; the pin is also a 5V-tolerant GPIO (PB11). |
| 61 | PB8/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ8, USART5_CK and EXMC_WE. |
| 62 | PB9/FG2 | bidirectional | 5V-tolerant GPIO (input must not exceed 5 V); alternate functions include EIRQ9, EMB_IN4 and EXMC_OE. |
| 63 | VSS | power_in | Power ground, 0 V. |
| 64 | VCC | power_in | Power supply, 1.8 V to 3.6 V; place decoupling capacitors close to the VSS pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XHSC |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC-VSS (incl. AVCC, VCC) | VCC-VSS | -0.3 | 4 | V | 40 | ||
| Total current into all VCCx supply lines (source) | ΣIVCC | 240 | mA | 40 | |||
| Maximum current into each VCCx supply line (source) | IVCC | 100 | mA | 40 | |||
| Total current out of all VSSx ground lines (sink) | ΣIVSS | -240 | mA | 40 | |||
| Maximum current out of each VSSx ground line (sink) | IVSS | -100 | mA | 40 | |||
| Output sink current on any I/O and control pin | IIO | 20 | mA | 40 | |||
| Output source current on any I/O and control pin | IIO | -20 | mA | 40 | |||
| Total output sink current, all I/O and control pins | ΣIIO | 120 | mA | Applies to 64-pin and larger packages (48-pin: 80 mA; 32-pin: 40 mA) | 40 | ||
| Total output source current, all I/O and control pins | ΣIIO | -120 | mA | Applies to 64-pin and larger packages (48-pin: -80 mA; 32-pin: -40 mA) | 40 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 40 | ||
| Maximum junction temperature range | TJ | -40 | 125 | °C | 40 | ||
| Internal AHB clock frequency, ultra-low-speed mode | fHCLK | 8 | MHz | PWRC2.DVS=0b10, PWRC3.DDAS=0b0000 | 34 | ||
| NRST reset minimum pulse width | TNRST | 10 | µs | 35 | |||
| Run current, all module clocks OFF, while(1) | ICC_RUN | 33 | mA | fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V | 44 | ||
| Run current, all module clocks ON, while(1) | ICC_RUN | 48 | mA | fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V | 44 | ||
| Dhrystone current, cache OFF | ICC_DHRYSTONE | 34 | mA | fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V | 44 | ||
| Sleep current, all module clocks OFF | ICC_SLEEP | 24 | mA | fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V | 44 | ||
| Sleep current, all module clocks ON | ICC_SLEEP | 39 | mA | fHCLK=200MHz, TA=105°C, VCC=1.8~3.6V | 44 | ||
| Flash supply current, read mode | IVCC | 5 | mA | VCC=1.8~3.6V | 45 | ||
| Flash supply current, program mode | IVCC | 10 | mA | VCC=1.8~3.6V | 45 | ||
| Flash supply current, block erase mode | IVCC | 10 | mA | VCC=1.8~3.6V | 45 | ||
| Flash supply current, full erase mode | IVCC | 10 | mA | VCC=1.8~3.6V | 45 | ||
| Oscillator frequency (XTAL crystal/resonator) | fXTAL_IN | 4 | 25 | MHz | 42 | ||
| HRC frequency accuracy | -2 | 2 | % | TA=-40~105°C | 44 | ||
| PLL PFD input clock frequency | fPLL_IN | 4 | 25 | MHz | 45 | ||
| Schmitt input hysteresis | VHYS | 0.1 | 0.2 | V | 1.8≤VCC≤3.6 | 47 | |
| I/O input leakage current | ILKG | 1 | µA | VSS≤VIN≤VCC | 47 | ||
| I/O input leakage current | ILKG | 10 | µA | VIN=5.5V | 47 | ||
| Weak pull-up equivalent resistance | RPU | 10 | 30 | 150 | kΩ | VIN=VSS, 1.8≤VCC≤3.6 | 47 |
| CMOS/Schmitt TTL-compatible input low level | TTL_VIL | 0.8 | V | 2.7≤VCC≤3.6 | 47 |
CAD (KiCad official)
- Symbol:
HC32F448KCTI-LQFP64 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
hc32f448kcti-lqfp64-etched.step/hc32f448kcti-lqfp64-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hc32f448kcti-lqfp64.step/hc32f448kcti-lqfp64.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XHSC datasheet (94 pp, sha256
69113ad72760a1d2, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).