ADUM5210ARSZ from Analog Devices, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD1	power_in	Power supply for the Side 1 logic circuits, independent of VDDP, operating between 3.135 V and 5.5 V.
2	GNDP	power_in	Ground reference for isolator Side 1; all GNDP pins are internally connected and should be tied to a common ground.
3	VIA	input	Logic Input A.
4	VIB	input	Logic Input B.
5	GNDP	power_in	Ground reference for isolator Side 1; all GNDP pins are internally connected and should be tied to a common ground.
6	GNDP	power_in	Ground reference for isolator Side 1; all GNDP pins are internally connected and should be tied to a common ground.
7	NC	unconnected	This pin is not connected internally.
8	PDIS	input	Power disable: logic low keeps the power converter active, logic high puts the power supply in low power standby mode.
9	VDDP	power_in	Primary isoPower supply voltage, 3.135 V to 5.5 V.
10	GNDP	power_in	Ground reference for isolator Side 1; all GNDP pins are internally connected and should be tied to a common ground.
11	GNDISO	power_in	Ground reference for isolator Side 2; all GNDISO pins are internally connected and should be tied to a common ground.
12	VISO	power_out	Secondary supply voltage output for external loads, 3.3 V (VSEL low) or 5.0 V (VSEL high).
13	VSEL	input	Output voltage select: use a thermally matched resistor network between VISO and GNDISO to divide the output to the 1.25 V reference; VISO can be programmed up to 20% higher or 75% lower than VDDP within the allowed output range.
14	NC	unconnected	This pin is not connected internally.
15	GNDISO	power_in	Ground reference for isolator Side 2; all GNDISO pins are internally connected and should be tied to a common ground.
16	GNDISO	power_in	Ground reference for isolator Side 2; all GNDISO pins are internally connected and should be tied to a common ground.
17	VOB	output	Logic Output B.
18	VOA	output	Logic Output A.
19	GNDISO	power_in	Ground reference for isolator Side 2; all GNDISO pins are internally connected and should be tied to a common ground.
20	VDD2	power_in	Power supply for the Side 2 logic circuits, independent of VISO, operating between 3.135 V and 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SSOP-20-208mil
Category	Power Management ICs
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VISO setpoint (5 V/5 V)	VISO	4.675	5	5.325	V	IISO = 15 mA, R1 = 10 kΩ, R2 = 30.9 kΩ	4
Load regulation (5 V/5 V)	VISO (LOAD)		1.3	3	%	IISO = 3 mA to 27 mA	4
IDDP no VISO load (5 V/5 V)	IDDP (Q)		6.8	12	mA		4
Output supply current (5 V/5 V)	IISO (MAX)	30			mA	5.5 V > VISO > 4.5 V	4
ADuM5210 IDD1, 1 Mbps (5 V)	IDD1		1.1	1.6	mA	CL = 0 pF	4
ADuM5210 IDD2, 1 Mbps (5 V)	IDD2		2.7	4.5	mA	CL = 0 pF	4
Data rate, A grade		1			Mbps	Within PWD limit	4
Propagation delay, A grade (5 V/5 V)	tPHL, tPLH			50	ns	50% input to 50% output	4
Pulse width distortion, A grade	PWD			10	ns	/tPLH − tPHL/	4
Pulse width, A grade	PW	1000			ns	Within PWD limit	4
Propagation delay skew, A grade	tPSK			38	ns	Between any two units	4
Channel matching codirectional, A grade	tPSKCD			5	ns		4
Channel matching opposing direction, A grade	tPSKOD			10	ns		4
Logic low output voltage	VOL		0	0.1	V	IOx = 20 µA, VIx = VIxL	5
Logic low output voltage	VOL		0.2	0.4	V	IOx = 3.2 mA, VIx = VIxL	5
Quiescent input supply current (5 V/5 V)	IDDI(Q)		0.54	0.8	mA		5
Quiescent output supply current (5 V/5 V)	IDDO(Q)		1.6	2	mA		5
Input current per channel	II	-10	0.01	10	µA	0 V ≤ VIx ≤ VDDx	5
Common-mode transient immunity (5 V/5 V)	/CM/	25	35		kV/µs	VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V	5
VISO setpoint (3.3 V/3.3 V)	VISO	3.135	3.3	3.51	V	IISO = 10 mA, R1 = 10 kΩ, R2 = 16.9 kΩ	5
Load regulation (3.3 V/3.3 V)	VISO (LOAD)		1.3	3	%	IISO = 2 mA to 18 mA	5
IDDP no VISO load (3.3 V/3.3 V)	IDDP (Q)		3.3	10.5	mA		6
Output supply current (3.3 V/3.3 V)	IISO (MAX)	20			mA	3.6 V > VISO > 3.135 V	6
ADuM5210 IDD1, 1 Mbps (3.3 V)	IDD1		0.75	1.4	mA	CL = 0 pF	6
ADuM5210 IDD2, 1 Mbps (3.3 V)	IDD2		2	3.5	mA	CL = 0 pF	6
Propagation delay, A grade (3.3 V/3.3 V)	tPHL, tPLH			50	ns	50% input to 50% output	6
Quiescent input supply current (3.3 V/3.3 V)	IDDI(Q)		0.4	0.6	mA		7
Quiescent output supply current (3.3 V/3.3 V)	IDDO(Q)		1.2	1.7	mA		7
VISO setpoint (5 V/3.3 V)	VISO	3.135	3.3	3.51	V	IISO = 15 mA, R1 = 10 kΩ, R2 = 16.9 kΩ	7
Load regulation (5 V/3.3 V)	VISO (LOAD)		1.3	3	%	IISO = 3 mA to 27 mA	7
IDDP no VISO load (5 V/3.3 V)	IDDP (Q)		3.2	8	mA		7
Output supply current (5 V/3.3 V)	IISO (MAX)	30			mA	3.6 V > VISO > 3.135 V	7
ADuM5210 IDD1, 1 Mbps (5 V/3.3 V)	IDD1		1.1	1.6	mA	CL = 0 pF	7
ADuM5210 IDD2, 1 Mbps (5 V/3.3 V)	IDD2		2	3.5	mA	CL = 0 pF	7
Propagation delay, A grade (5 V/3.3 V)	tPHL, tPLH			50	ns	50% input to 50% output	8
Quiescent input supply current (5 V/3.3 V)	IDDI(Q)		0.54	0.75	mA		8
Quiescent output supply current (5 V/3.3 V)	IDDO(Q)		1.2	2	mA		8
Operating temperature	TA	-40		105	°C		11
VDDP supply	VDDP	3.135		5.5	V	VISO = 3.135 V to 3.6 V	11
VDDP supply	VDDP	4.5		5.5	V	VISO = 4.5 V to 5.5 V	11
VDD1, VDD2 supply	VDD1, VDD2	3.135		5.5	V		11
Storage temperature	TST	-55		150	°C		12
Supply voltages	VDDP, VDD1, VDD2, VISO	-0.5		7	V	relative to respective ground	12
VISO supply current				30	mA	TA = −40°C to +105°C	12
Average output current per data output pin		-10		10	mA		12
Common-mode transients		-100		100	kV/µs		12
Junction-to-air thermal impedance	θJA		50		°C/W	See the Thermal Analysis section	9
VISO thermal coefficient (5 V/5 V)	VISO (TC)		-44		μV/°C		4
Switching frequency	fOSC		125		MHz		4
Thermal shutdown temperature			154		°C		4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		5 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up	12

CAD (KiCad official)

Symbol: ADUM5210ARSZ
Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
3D model: SSOP-20-208mil (KiCad packages3D, STEP)
3D model files: adum5210arsz-etched.step / adum5210arsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adum5210arsz.step / adum5210arsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (23 pp, sha256 e4c5c82979591a34, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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ADUM5210ARSZ

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