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SN74LV165AMPWREP
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LV165AMPWREP
Texas Instruments · Shift Registers · TSSOP-16
SN74LV165AMPWREP from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SH/LD | input | Shift/load control: a low level enables the parallel data inputs A through H, and a high level inhibits parallel loading. |
| 2 | CLK | input | Clock input: clocking occurs on a low-to-high transition while SH/LD is high and CLK INH is low. |
| 3 | E | input | Parallel data input E, loaded into the register while SH/LD is low. |
| 4 | F | input | Parallel data input F, loaded into the register while SH/LD is low. |
| 5 | G | input | Parallel data input G, loaded into the register while SH/LD is low. |
| 6 | H | input | Parallel data input H, loaded into the register while SH/LD is low. |
| 7 | ~{QH} | output | Complemented serial output of the register (QH-bar); unused inputs elsewhere must be tied to VCC or GND per the recommended operating conditions. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | QH | output | Serial output QH; data shifts toward this pin when the device is clocked. |
| 10 | SER | input | Serial data input, shifted into the register on each valid clock transition. |
| 11 | A | input | Parallel data input A, loaded into the register while SH/LD is low. |
| 12 | B | input | Parallel data input B, loaded into the register while SH/LD is low. |
| 13 | C | input | Parallel data input C, loaded into the register while SH/LD is low. |
| 14 | D | input | Parallel data input D, loaded into the register while SH/LD is low. |
| 15 | CLK INH | input | Clock inhibit input: functionally interchangeable with CLK, and should change to high only while CLK is high. |
| 16 | VCC | power_in | Supply voltage, 2 V to 5.5 V per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LV165AMPWREP - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74lv165ampwrep-etched.step/sn74lv165ampwrep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv165ampwrep.step/sn74lv165ampwrep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (13 pp, sha256
011ad638fdf3f2b5, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).