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LMH1297RTVR

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Texas Instruments Video Interface ICs, WQFN-32-EP(5x5). Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Contents

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LMH1297RTVR

Texas Instruments · Video Interface ICs · WQFN-32-EP(5x5)

LMH1297RTVR from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDI_IO+ bidirectional Bidirectional 75-Ω single-ended video I/O with integrated return loss network, functions as 75-Ω input in EQ mode or 75-Ω output in CD mode for SMPTE video rates to 11.88 Gbps.
2 SDI_IO- bidirectional Bidirectional 75-Ω complement to SDI_IO+ requiring external 4.7-µF AC-coupling capacitor and 75-Ω termination to GND.
3 VSS power_in Ground reference.
4 OUT0_SEL input LVCMOS input internally pulled high to enable 100-Ω host-side output driver at OUT0±.
5 EQ/CD_SEL input LVCMOS input internally pulled low to select I/O mode: low for EQ mode (adaptive equalizer), high for CD mode (cable driver).
6 VSS power_in Ground reference.
7 SDI_OUT- output Analog 75-Ω single-ended output with integrated return loss network requiring external 4.7-µF AC-coupling capacitor and 75-Ω termination to GND.
8 SDI_OUT+ output Analog 75-Ω single-ended primary output serving as loop-through in EQ mode or secondary cable driver in CD mode.
9 HOST_EQ0 input 4-LEVEL input selecting driver output amplitude and de-emphasis level for OUT0± in EQ mode or IN0± equalizer boost in CD mode.
10 RSV1 unconnected Reserved pin; do not connect.
11 SS_N_ADDR0 input Dual-function SPI target select input (active low, internally pulled high) or 4-LEVEL SMBus address strap ADDR0.
12 MODE_SEL input 4-LEVEL input selecting control interface mode: SPI (float) or SMBus (low).
13 MOSI_SDA bidirectional Dual-function 2.5-V LVCMOS input (MOSI in SPI mode) or 3.3-V tolerant open-drain bidirectional data line (SDA in SMBus mode).
14 SDI_OUT_SEL input LVCMOS input internally pulled high to disable 75-Ω output driver at SDI_OUT±.
15 RSV2 unconnected Reserved pin; do not connect.
16 RSV3 unconnected Reserved pin; do not connect.
17 OUT_CTRL input 4-LEVEL input selecting output signal routing and enabling or bypassing reclocker and cable equalizer.
18 IN0- input Analog 100-Ω differential input from host video processor with on-chip termination, requires external 4.7-µF AC-coupling capacitor for SMPTE applications.
19 IN0+ input Analog 100-Ω differential complement to IN0- with on-chip termination, requires external 4.7-µF AC-coupling capacitor for SMPTE applications.
20 VSS power_in Ground reference.
21 VDD_CDR power_in Power input, 2.5-V ± 5% supply for reclocker circuitry, requires 0.1-µF bypass capacitor close to pin.
22 OUT0- output Analog 100-Ω differential output to host video processor with on-chip termination, requires external 4.7-µF AC-coupling capacitor for SMPTE applications.
23 OUT0+ output Analog 100-Ω differential complement to OUT0- with on-chip termination, requires external 4.7-µF AC-coupling capacitor for SMPTE applications.
24 SDI_VOD input 4-LEVEL input selecting cable driver output amplitude for SDI_IO± and SDI_OUT±: H = +5%, F = nominal (800 mVp-p), R = +10%, L = -5%.
25 RSV5 unconnected Reserved pin; do not connect.
26 RSV4 unconnected Reserved pin; do not connect.
27 LOCK_N output 3.3-V tolerant open-drain output (active low) providing reclocker lock indicator when CDR acquires lock, reconfigurable through register for CD_N or INT_N.
28 MISO_ADDR1 output Dual-function 2.5-V LVCMOS output (MISO in SPI mode) or 4-LEVEL SMBus address strap ADDR1.
29 SCK_SCL input Dual-function 2.5-V LVCMOS input (SCK in SPI mode) or 3.3-V tolerant open-drain bidirectional clock line (SCL in SMBus mode) requiring external pullup resistor.
30 VIN power_in Power input, 2.5-V ± 5% external supply, requires 10-µF and 1-µF bulk decoupling capacitors.
31 VDD_LDO power_out Power output, 1.8-V internal LDO regulator output requiring 1-µF and 0.1-µF bypass capacitors to VSS.
32 ENABLE input LVCMOS input internally pulled high to enable normal operation (high) or force Power-Down mode (low).
EP EP power_in Exposed thermal pad connected to VSS ground plane through 3×3 via array for thermal and mechanical performance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-32-EP(5x5)
Category Interface
Pins 33

CAD (KiCad official)

  • Symbol: LMH1297RTVR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: lmh1297rtvr-etched.step / lmh1297rtvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lmh1297rtvr.step / lmh1297rtvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 2dc0a821b809e09a, retrieved 2026-09-29, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF