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SN65LVDM050D

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Texas Instruments LVDS ICs, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN65LVDM050D

Texas Instruments · LVDS ICs · SOIC-16

SN65LVDM050D from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1B input Channel 1 inverting differential receiver input (LVDS), which detects a 50 mV differential with up to 1 V ground potential difference.
2 1A input Channel 1 non-inverting differential receiver input (LVDS), which detects a 50 mV differential with up to 1 V ground potential difference.
3 1R output Channel 1 receiver logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when the inputs are open (failsafe).
4 RE input Receiver enable input shared by both receivers (LVTTL levels are 5-V tolerant).
5 2R output Channel 2 receiver logic output, high for VID ≥ 50 mV, low for VID ≤ -50 mV, and high when the inputs are open (failsafe).
6 2A input Channel 2 non-inverting differential receiver input (LVDS), which detects a 50 mV differential with up to 1 V ground potential difference.
7 2B input Channel 2 inverting differential receiver input (LVDS), which detects a 50 mV differential with up to 1 V ground potential difference.
8 GND power_in Ground.
9 2D input Channel 2 driver logic input (LVTTL levels are 5-V tolerant).
10 2Y output Channel 2 non-inverted differential driver output (LVDS, about 340 mV typical into a 50-Ω load), high impedance when disabled or with VCC < 1.5 V.
11 2Z output Channel 2 inverted differential driver output (LVDS, about 340 mV typical into a 50-Ω load), high impedance when disabled or with VCC < 1.5 V.
12 DE input Driver enable input shared by both drivers; drivers are high impedance when disabled.
13 1Z output Channel 1 inverted differential driver output (LVDS, about 340 mV typical into a 50-Ω load), high impedance when disabled or with VCC < 1.5 V.
14 1Y output Channel 1 non-inverted differential driver output (LVDS, about 340 mV typical into a 50-Ω load), high impedance when disabled or with VCC < 1.5 V.
15 1D input Channel 1 driver logic input (LVTTL levels are 5-V tolerant).
16 VCC power_in Single 3.3-V supply input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: SN65LVDM050D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn65lvdm050d-etched.step / sn65lvdm050d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvdm050d.step / sn65lvdm050d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 da1071ed34b491ab, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF