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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ESP32-S3FN8

Espressif Systems · Microcontrollers (MCU/MPU/SOC) · QFN-56-EP(7x7)

ESP32-S3FN8 from Espressif Systems, in a QFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LNA_IN	bidirectional	RF low-noise amplifier input/output for the 2.4 GHz receiver, an analog RF port rather than a digital GPIO.
2	VDD3P3	power_in	Analog power supply (analog domain), recommended 3.0-3.6 V with 3.3 V typical.
3	VDD3P3	power_in	Analog power supply (analog domain), recommended 3.0-3.6 V with 3.3 V typical.
4	CHIP_PU	input	Chip enable: high activates the chip, low powers it down, and the pin must not be left floating.
5	GPIO0	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with weak pull-up at reset; strapping pin that, together with GPIO46, selects the boot mode (GPIO0 high for SPI Boot, low with GPIO46 low for Joint Download Boot).
6	GPIO1	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO1, TOUCH1 and ADC1_CH0 functions; has a ~60 µs low glitch at power-on.
7	GPIO2	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO2, TOUCH2 and ADC1_CH1 functions; has a ~60 µs low glitch at power-on.
8	GPIO3	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO3, TOUCH3 and ADC1_CH2 functions; it is the JTAG-source strapping pin and has no internal pull resistors, so it must be driven by an external circuit that is not high-impedance.
9	GPIO4	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO4, TOUCH4 and ADC1_CH3 functions.
10	GPIO5	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO5, TOUCH5 and ADC1_CH4 functions.
11	GPIO6	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO6, TOUCH6 and ADC1_CH5 functions.
12	GPIO7	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO7, TOUCH7 and ADC1_CH6 functions.
13	GPIO8	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also providing RTC_GPIO8, TOUCH8 and ADC1_CH7 functions, and SUBSPICS1 on IO MUX F4.
14	GPIO9	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO9, TOUCH9 and ADC1_CH8 functions.
15	GPIO10	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO10, TOUCH10 and ADC1_CH9 functions.
16	GPIO11	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO11, TOUCH11 and ADC2_CH0 functions.
17	GPIO12	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO12, TOUCH12 and ADC2_CH1 functions.
18	GPIO13	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO13, TOUCH13 and ADC2_CH2 functions.
19	GPIO14	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO14, TOUCH14 and ADC2_CH3 functions.
20	VDD3P3_RTC	power_in	Supply for the RTC and part of the digital domain (RTC IOs), recommended 3.0-3.6 V.
21	XTAL_32K_P	bidirectional	Positive terminal of the external 32 kHz crystal (or 32 kHz clock input) on the VDD3P3_RTC domain, also usable as GPIO15/RTC_GPIO15 and ADC2_CH4.
22	XTAL_32K_N	bidirectional	Negative terminal of the external 32 kHz crystal (or 32 kHz clock input) on the VDD3P3_RTC domain, also usable as GPIO16/RTC_GPIO16 and ADC2_CH5.
23	GPIO17	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO17, ADC2_CH6 and U1TXD; default drive current 10 mA.
24	GPIO18	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with input enable, also providing RTC_GPIO18, ADC2_CH7, U1RXD and CLK_OUT3; default drive current 10 mA.
25	GPIO19	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also used as USB_D- by default; default drive current 40 mA and it emits two ~60 µs high glitches at power-on.
26	GPIO20	bidirectional	General-purpose I/O on the VDD3P3_RTC domain also used as USB_D+ with USB pull-up control by default; default drive current 40 mA and it emits high glitches at power-on.
27	GPIO21	bidirectional	General-purpose I/O on the VDD3P3_RTC domain with RTC_GPIO21 function and no analog function.
28	SPICS1	bidirectional	SPI chip-select 1 (CS1) for in-package PSRAM on the VDD_SPI domain, usable as GPIO26 via IO MUX; the datasheet advises against using flash/PSRAM pins for other purposes.
29	VDD_SPI	power_in	Power pin for the SPI flash/PSRAM IO domain, which the datasheet lists as 3.3 V for ESP32-S3FN8; it can also act as a regulator output when driving external 1.8 V flash.
30	SPIHD	bidirectional	Hold signal (HOLD# / SIO3) for in-package Quad SPI flash on the VDD_SPI domain; not recommended for other uses.
31	SPIWP	bidirectional	Write-protect signal (WP# / SIO2) for in-package Quad SPI flash on the VDD_SPI domain; not recommended for other uses.
32	SPICS0	bidirectional	Chip-select 0 (CS#) for in-package flash on the VDD_SPI domain; not recommended for other uses.
33	SPICLK	bidirectional	Clock output to in-package flash (CLK) on the VDD_SPI domain; not recommended for other uses.
34	SPIQ	bidirectional	Data output (DO / SIO1) for in-package Quad SPI flash on the VDD_SPI domain; not recommended for other uses.
35	SPID	bidirectional	Data input (DI / SIO0) for in-package Quad SPI flash on the VDD_SPI domain; not recommended for other uses.
36	SPICLK_N	bidirectional	Negative differential SPI clock used in octal SPI modes, powered from VDD_SPI or VDD3P3_CPU per eFuse; alternatively GPIO48.
37	SPICLK_P	bidirectional	Positive differential SPI clock used in octal SPI modes, powered from VDD_SPI or VDD3P3_CPU per eFuse; alternatively GPIO47.
38	GPIO33	bidirectional	General-purpose I/O on the VDD_SPI / VDD3P3_CPU domain with input enable; used as DQ4 only in octal flash/PSRAM mode.
39	GPIO34	bidirectional	General-purpose I/O on the VDD_SPI / VDD3P3_CPU domain with input enable; used as DQ5 only in octal flash/PSRAM mode.
40	GPIO35	bidirectional	General-purpose I/O on the VDD_SPI / VDD3P3_CPU domain with input enable; used as DQ6 only in octal flash/PSRAM mode.
41	GPIO36	bidirectional	General-purpose I/O on the VDD_SPI / VDD3P3_CPU domain with input enable; used as DQ7 only in octal flash/PSRAM mode.
42	GPIO37	bidirectional	General-purpose I/O on the VDD_SPI / VDD3P3_CPU domain with input enable; used as DQS/DM only in octal flash/PSRAM mode.
43	GPIO38	bidirectional	General-purpose I/O on the VDD3P3_CPU domain with input enable; also FSPIWP and SUBSPIWP function, and VMO when an external USB PHY is used.
44	MTCK	bidirectional	JTAG test clock on the VDD3P3_CPU domain, also usable as GPIO39 and CLK_OUT3.
45	MTDO	bidirectional	JTAG test data output on the VDD3P3_CPU domain, also usable as GPIO40 and CLK_OUT2.
46	VDD3P3_CPU	power_in	Supply for the digital CPU IO domain, recommended 3.0-3.6 V.
47	MTDI	bidirectional	JTAG test data input on the VDD3P3_CPU domain, also usable as GPIO41 and CLK_OUT1.
48	MTMS	bidirectional	JTAG test mode select on the VDD3P3_CPU domain, also usable as GPIO42.
49	U0TXD	bidirectional	UART0 transmit on the VDD3P3_CPU domain, with weak pull-up at reset and also usable as GPIO43.
50	U0RXD	bidirectional	UART0 receive on the VDD3P3_CPU domain, with weak pull-up at reset and also usable as GPIO44.
51	GPIO45	bidirectional	Strapping pin with weak pull-down at reset that selects the VDD_SPI voltage, on the VDD3P3_CPU domain.
52	GPIO46	bidirectional	Strapping pin with weak pull-down at reset that, with GPIO0, selects the boot mode and controls ROM log printing, on the VDD3P3_CPU domain.
53	XTAL_N	passive	Negative terminal of the external crystal (active or passive) or external clock input/output for the main oscillator.
54	XTAL_P	passive	Positive terminal of the external crystal (active or passive) or external clock input/output for the main oscillator.
55	VDDA	power_in	Analog power supply (analog domain), recommended 3.0-3.6 V.
56	VDDA	power_in	Analog power supply (analog domain), recommended 3.0-3.6 V.
57	GND	power_in	External ground; the datasheet lists this as the ground pin of the package.

Key specifications

Parameter	Value
Manufacturer	Espressif Systems
Package	QFN-56-EP(7x7)
Category	Embedded Processors & Controllers
Pins	57

CAD (KiCad official)

Symbol: ESP32-S3FN8
Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
3D model: QFN-56-EP(7x7) (KiCad packages3D, STEP)
3D model files: esp32-s3fn8-etched.step / esp32-s3fn8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); esp32-s3fn8.step / esp32-s3fn8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Espressif Systems datasheet (79 pp, sha256 97b4b3199f87c43f, retrieved 2026-10-10, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF