component
TPS3808G09DBVT
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS3808G09DBVT
Texas Instruments · Supervisor And Reset ICs · SOT-23-6
TPS3808G09DBVT from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | RESET is an open-drain output driven to a low-impedance state when SENSE is below VIT or MR is low, and it needs a pull-up resistor of 10kΩ to 1MΩ, which allows it to reach voltages higher than VDD. |
| 2 | GND | power_in | Ground reference for the device, to be connected to the ground plane. |
| 3 | MR | input | Driving the manual reset pin low asserts RESET, and MR is internally tied to VDD by a 90kΩ pull-up resistor. |
| 4 | CT | input | Reset period programming pin: connecting it to VDD through a 40kΩ to 200kΩ resistor or leaving it open gives fixed delay times, while a ground-referenced capacitor of 100pF or more gives a user-programmable delay. |
| 5 | SENSE | input | Connected to the voltage to be monitored, and RESET is asserted if this voltage drops below the threshold voltage VIT. |
| 6 | VDD | power_in | Supply voltage input, with a 0.1μF ceramic capacitor recommended close to this pin for good analog design practice. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Input supply range | VDD | 1.7 | 6.5 | V | -40°C < TJ < 125°C | 6 | |
| VDD Input supply range | VDD | 1.65 | 6.5 | V | 0°C < TJ < 85°C | 6 | |
| Supply current (current into VDD pin) | IDD | 2.4 | 5 | μA | VDD = 3.3V, RESET not asserted, MR, RESET, CT open | 6 | |
| Supply current (current into VDD pin) | IDD | 2.7 | 6 | μA | VDD = 6.5V, RESET not asserted, MR, RESET, CT open | 6 | |
| Low-level output voltage | VOL | 0.3 | V | 1.3V ≤ VDD < 1.8V, IOL = 0.4mA | 6 | ||
| Low-level output voltage | VOL | 0.4 | V | 1.8V ≤ VDD ≤ 6.5V, IOL = 1mA | 6 | ||
| Negative-going input threshold accuracy | VIT | -1.5 | 0.5 | 1.5 | % | VIT ≤ 3.3V | 6 |
| Negative-going input threshold accuracy | VIT | -1.25 | 0.5 | 1.25 | % | VIT ≤ 3.3V, -40°C < TJ < 85°C | 6 |
| Hysteresis on VIT pin | VHYS | 1 | 2.5 | % | Fixed versions | 6 | |
| MR internal pullup resistance | RMR | 70 | 90 | kΩ | 6 | ||
| Reset delay time | td | 12 | 20 | 28 | ms | CT = Open, See Figure 6-1 | 7 |
| Reset delay time | td | 180 | 300 | 420 | ms | CT = VDD | 7 |
| Reset delay time | td | 0.75 | 1.25 | 1.75 | s | CT = 130pF | 7 |
| Reset delay time | td | 0.62 | 1.03 | 1.44 | s | CT = 180nF | 7 |
| VDD Input supply range (recommended) | VDD | 1.7 | 6.5 | V | Over operating free-air temperature range | 5 | |
| SENSE pin voltage (recommended) | VSENSE | 0 | 6.5 | V | Over operating free-air temperature range | 5 | |
| MR pin voltage (recommended) | VMR | 0 | 6.5 | V | Over operating free-air temperature range | 5 | |
| RESET pin voltage (recommended) | VRESET | 0 | 6.5 | V | Over operating free-air temperature range | 5 | |
| RESET pin current (recommended) | IRESET | 0.0003 | 5 | mA | Over operating free-air temperature range | 5 | |
| Voltage VDD (absolute maximum) | VDD | -0.3 | 7 | V | Over operating junction temperature range | 5 | |
| Voltage VCT (absolute maximum) | VCT | -0.3 | V | Upper limit VDD + 0.3 V | 5 | ||
| Voltage VRESET, VMR, VSENSE (absolute maximum) | VRESET, VMR, VSENSE | -0.3 | 7 | V | Over operating junction temperature range | 5 | |
| Current RESET pin (absolute maximum) | IRESET | -5 | 5 | mA | Over operating junction temperature range | 5 | |
| Operating junction temperature (absolute maximum) | TJ | -40 | 150 | °C | Over operating junction temperature range | 5 | |
| Storage temperature (absolute maximum) | Tstg | -65 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 180.9 | °C/W | DBV (SOT-23) 6 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 117.8 | °C/W | DBV (SOT-23) 6 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 27.8 | °C/W | DBV (SOT-23) 6 pins | 5 | ||
| Junction-to-top characterization parameter | ψJT | 18.9 | °C/W | DBV (SOT-23) 6 pins | 5 | ||
| Junction-to-board characterization parameter | ψJB | 27.3 | °C/W | DBV (SOT-23) 6 pins | 5 |
CAD (KiCad official)
- Symbol:
TPS3808G09DBVT - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tps3808g09dbvt-etched.step/tps3808g09dbvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3808g09dbvt.step/tps3808g09dbvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
74d889c0f68af880, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).