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LMR33630ADDAR
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Texas Instruments DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownLMR33630ADDAR
Texas Instruments · DC-DC Converters · ESOP-8
LMR33630ADDAR from Texas Instruments, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short, wide traces to minimize input-loop inductance. |
| 2 | VIN | power_in | Input supply to the regulator, 3.8 V to 36 V (38 V abs max). Connect a high-quality bypass capacitor directly between this pin and PGND with short, wide traces. |
| 3 | EN | input | Enable input to the regulator. High = ON, low = OFF; precision-threshold input. Can be tied directly to VIN. Must not exceed VIN by more than 0.3 V. Do not float. |
| 4 | PG | output | Open-drain power-good flag output (22 V abs max, 18 V recommended). Connect to a suitable voltage supply through a current-limiting resistor. High = power OK, low = power bad. Flag pulls low when EN = low. May be left open when not used. |
| 5 | FB | input | Feedback input to the regulator. Connect to the tap point of the external feedback voltage divider that sets VOUT (1 V to 24 V). Internal reference is approximately 1 V. Do not float, do not ground. |
| 6 | VCC | power_out | Internal 5-V LDO output used as supply for internal control circuits. Do not connect to external loads. Can be used as logic supply for the power-good pull-up. Connect a high-quality 1-µF ceramic capacitor from this pin to GND. |
| 7 | BOOT | power_in | Boot-strap supply voltage for the internal high-side gate driver. Connect a high-quality 100-nF ceramic capacitor between this pin and the SW pin (BOOT-to-SW abs max 5.5 V). |
| 8 | SW | power_out | Regulator switch node. Connect to the power inductor. Also returns the bootstrap capacitor current. High-dV/dt node - keep the trace short and away from sensitive nodes. |
| 9 | AGND | power_in | Analog ground / thermal pad on the bottom of the HSOIC package. Ground reference for internal references and logic; all electrical parameters are measured with respect to this pin. Serves as both AGND connection and the primary thermal path - must be soldered to a ground plane for proper electrical and thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
LMR33630ADDARLMR33630ADDARBDDALMR33630ADDARBDDARLMR33630ADDARCDDALMR33630ADDARCDDARLMR33630ADDARNXLMR33630ADDARNXRLMR33630ADDARBRNXLMR33630ADDARBRNXRLMR33630ADDARCRNXLMR33630ADDARCRNXR
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to PGND | VIN | -0.3 | 38 | V | 5 | ||
| EN to AGND | EN | -0.3 | V | 5 | |||
| FB to AGND | FB | -0.3 | 5.5 | V | 5 | ||
| PG to AGND | PG | 0 | 22 | V | 5 | ||
| AGND to PGND | AGND-PGND | -0.3 | 0.3 | V | 5 | ||
| SW to PGND | SW | -0.3 | V | 5 | |||
| SW to PGND transient | SW | -3.5 | 38 | V | less than 100-ns transients | 5 | |
| BOOT to SW | BOOT-SW | -0.3 | 5.5 | V | 5 | ||
| VCC to AGND | VCC | -0.3 | 5.5 | V | 5 | ||
| Junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| Input voltage VIN to PGND | VIN | 3.8 | 36 | V | 5 | ||
| EN voltage | EN | 0 | V | 5 | |||
| PG voltage | PG | 0 | 18 | V | 5 | ||
| Adjustable output voltage | VOUT | 1 | 24 | V | 5 | ||
| Output current | IOUT | 0 | 3 | A | 5 | ||
| Recommended operating temperature range | -40 | 125 | °C | Recommended operating temperature range (table header) | 5 | ||
| Minimum operating input voltage | VIN | 3.8 | V | 6 | |||
| Non-switching input current | IQ | 24 | 34 | µA | VFB = 1.2 V | 6 | |
| Shutdown quiescent current | ISD | 5 | 10 | µA | EN = 0 | 6 | |
| EN input level to start switching (rising threshold) | VEN-H | 1.2 | 1.231 | 1.26 | V | Rising threshold | 6 |
| EN hysteresis below VEN-H | VEN-HYS | 100 | mV | Hysteresis below VEN-H; falling | 6 | ||
| EN input level to turn on internal LDO (rising threshold) | VEN-VCC-H | 1 | V | Rising threshold | 6 | ||
| Internal LDO output voltage at VCC pin | VCC | 4.75 | 5 | 5.25 | V | 6 V ≤ VIN ≤ 36 V | 6 |
| Feedback voltage (ADJ option) | VFB | 0.985 | 1 | 1.015 | V | ADJ option | 6 |
| Current into FB pin (ADJ option) | IFB | 0.2 | 50 | nA | ADJ option; FB = 1 V | 6 | |
| High-side current limit | ISC | 3.85 | 4.5 | 5.05 | A | LMR33630 | 6 |
| Low-side current limit | ILIMIT | 2.9 | 3.5 | 4.1 | A | LMR33630 | 6 |
| Minimum peak inductor current | IPEAK-MIN | 0.69 | A | LMR33630 | 6 | ||
| Zero current detector threshold | IZC | -0.106 | A | 7 | |||
| Internal soft-start time | tSS | 2.9 | 4 | 6 | ms | 7 | |
| Power-good upper threshold rising (% of FB voltage) | VPG-HIGH-UP | 105 | 107 | 110 | % | 7 | |
| Power-good upper threshold falling (% of FB voltage) | VPG-HIGH-DN | 103 | 105 | 108 | % | 7 | |
| Power-good lower threshold rising (% of FB voltage) | VPG-LOW-UP | 92 | 94 | 97 | % | 7 | |
| Power-good lower threshold falling (% of FB voltage) | VPG-LOW-DN | 90 | 92 | 95 | % | 7 | |
| Power-good glitch filter delay | tPG | 60 | 170 | µs | 7 | ||
| Power-good flag RDSON | RPG | 76 | 150 | Ω | VIN = 12 V, VEN = 4 V | 7 | |
| Power-good flag RDSON | RPG | 35 | 60 | Ω | VEN = 0 V | 7 | |
| Minimum input voltage for proper PG function | VIN-PG | 2 | V | 50-µA, EN = 0 V | 7 | ||
| Switching frequency A version | ƒSW | 340 | 400 | 460 | kHz | A version | 7 |
| High-side MOSFET ON-resistance, DDA package | RDS-ON-HS | 95 | 160 | mΩ | DDA package | 7 | |
| Low-side MOSFET ON-resistance, DDA package | RDS-ON-LS | 66 | 110 | mΩ | DDA package | 7 | |
| Minimum switch on-time, DDA package | tON-MIN | 75 | 108 | ns | DDA package | 7 | |
| Minimum switch off-time, DDA package | tOFF-MIN | 50 | 85 | ns | DDA package | 7 | |
| Maximum switch on-time | tON-MAX | 7 | 9 | µs | 7 | ||
| Input supply current when in regulation | ISUPPLY | 25 | µA | VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A, RFBT = 1 MΩ | 8 | ||
| Dropout voltage (VIN - VOUT) | VDROP | 150 | mV | VOUT = 5 V, IOUT = 1 A; dropout at -1% of regulation, fSW = 140 kHz | 8 | ||
| Output voltage regulation, VOUT = 5 V, full load | VOUT | -1.5 | 2.5 | % | VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A to max. load | 8 | |
| Output voltage regulation, VOUT = 5 V, 1 A to full load | VOUT | -1.5 | 1.5 | % | VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A to max. load | 8 | |
| Output voltage regulation, VOUT = 3.3 V, full load | VOUT | -1.5 | 2.5 | % | VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 0 A to max. load | 8 | |
| Output voltage regulation, VOUT = 3.3 V, 1 A to full load | VOUT | -1.5 | 1.5 | % | VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT = 1 A to max. load | 8 | |
| Thermal shutdown temperature | TSD | 165 | °C | Shutdown temperature | 8 | ||
| Bootstrap voltage undervoltage lock-out threshold | VBOOT-UVLO | 2.2 | V | 6 | |||
| Junction-to-ambient thermal resistance | RθJA | 42.9 | °C/W | JESD 51-7, 4-layer JEDEC board; DDA (8-pin HSOIC) | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 54 | °C/W | JESD 51-7, 4-layer JEDEC board; DDA (8-pin HSOIC) | 6 | ||
| Junction-to-board thermal resistance | RθJB | 13.6 | °C/W | JESD 51-7, 4-layer JEDEC board; DDA (8-pin HSOIC) | 6 | ||
| Junction-to-top characterization parameter | ψJT | 4.3 | °C/W | JESD 51-7, 4-layer JEDEC board; DDA (8-pin HSOIC) | 6 | ||
| Junction-to-board characterization parameter | ψJB | 13.8 | °C/W | JESD 51-7, 4-layer JEDEC board; DDA (8-pin HSOIC) | 6 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 4.3 | °C/W | JESD 51-7, 4-layer JEDEC board; DDA (8-pin HSOIC) | 6 |
CAD (KiCad official)
- Symbol:
LMR33630ADDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
lmr33630addar-etched.step/lmr33630addar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lmr33630addar.step/lmr33630addar.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
lmr33630addar.step |
193 KB | You want the bare part, or you mark your own boards. |
lmr33630addar-etched.step |
2.5 MB | You want the part with LMR33630ADDAR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 615 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (53 pp, sha256
63404cdc9372a289, retrieved 2026-08-17, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).