component
UCC21550BDWR
Public Made by Adomby adom
Texas Instruments Others, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownUCC21550BDWR
Texas Instruments · Others · SOIC-16
UCC21550BDWR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INA | input | Input signal for A channel with TTL/CMOS compatible threshold, pulled low internally if left open; an RC filter of R = 10 Ω to 100 Ω and C = 10 pF to 100 pF is recommended. |
| 2 | INB | input | Input signal for B channel with TTL/CMOS compatible threshold, pulled low internally if left open; an RC filter of R = 10 Ω to 100 Ω and C = 10 pF to 100 pF is recommended. |
| 3 | VCCI | power_in | Primary-side supply voltage (3.0 V to 5.5 V recommended), to be decoupled locally to GND with a low ESR/ESL capacitor close to the device. |
| 4 | GND | power_in | Primary-side ground reference to which all primary-side signals are referenced. |
| 5 | DIS | input | Disables both driver outputs when high and enables both when low, internally pulled high if floating, and recommended to be tied to ground if unused (RC filter R = 0 Ω to 100 Ω, C = 100 pF to 1000 pF when driven from a microcontroller). |
| 6 | DT | input | Dead time programming pin: floating or shorted to VCCI disables the interlock, a 1.7 kΩ to 100 kΩ resistor to GND sets minimum dead time, and 0 Ω to 150 Ω or a short to GND interlocks the outputs; no ceramic capacitor above 1 nF is recommended. |
| 7 | NC | unconnected | No internal connection. |
| 8 | VCCI | power_in | Primary-side supply voltage, internally shorted to pin 3. |
| 9 | VSSB | power_in | Ground reference for secondary side B channel. |
| 10 | OUTB | output | Output of driver B, connected to the gate of the B channel transistor through a gate resistor. |
| 11 | VDDB | power_in | Secondary-side power for driver B (9.2 V to 25 V recommended for the B version), decoupled locally to VSSB with a low ESR/ESL capacitor close to the device. |
| 12 | NC | unconnected | No internal connection. |
| 13 | NC | unconnected | No internal connection. |
| 14 | VSSA | power_in | Ground reference for secondary side A channel. |
| 15 | OUTA | output | Output of driver A, connected to the gate of the A channel transistor through a gate resistor. |
| 16 | VDDA | power_in | Secondary-side power for driver A (9.2 V to 25 V recommended for the B version), decoupled locally to VSSA with a low ESR/ESL capacitor close to the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Others |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input bias supply voltage | VCCI | 3 | 5.5 | V | 5 | ||
| Output bias supply voltage (UCC21550B, 8V UVLO) | VDDA, VDDB | 9.2 | 25 | V | VDDA-VSSA, VDDB-VSSB | 5 | |
| Junction temperature (recommended) | TJ | -40 | 150 | ℃ | 5 | ||
| Input bias supply voltage (abs max) | VCCI | -0.3 | 6 | V | VCCI to GND | 5 | |
| Output bias supply voltage (abs max) | VDDA, VDDB | -0.3 | 30 | V | VDDA, VDDB to VSS | 5 | |
| Output signal transient voltage min | OUTA/OUTB | -2 | V | for 200 ns; max VDDA/B + 0.3 | 5 | ||
| Junction temperature (abs max) | TJ | -40 | 150 | ℃ | 5 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | JESD22-C101, all pins | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 69.8 | °C/W | DW 16 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 33.1 | °C/W | DW 16 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 36.9 | °C/W | DW 16 pins | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 22.2 | °C/W | DW 16 pins | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 36 | °C/W | DW 16 pins | 6 | ||
| VCC quiescent current | IVCC | 1.4 | 2 | mA | VINx = 0 V, DIS = GND; VCC=3.3V (same limits at 5V) | 9 | |
| VCC quiescent current | IVCC | 4.2 | 4.8 | mA | VINx = VCC, DIS = GND; VCC=3.3V (same limits at 5V) | 9 | |
| VCC quiescent current | IVCC | 2.7 | 3.2 | mA | VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND; VCC=3.3V (same at 5V) | 9 | |
| VDDx quiescent current | IVDDx | 1.2 | 2 | mA | VINx = 0 V, DIS = GND | 9 | |
| VDDx quiescent current | IVDDx | 1.4 | 2.3 | mA | VINx = 0 V, DIS = GND; VDD=25V | 9 | |
| VDDx quiescent current | IVDDx | 1.4 | 2.2 | mA | VINx = VCC, DIS = GND | 9 | |
| VDDx quiescent current | IVDDx | 1.5 | 2.5 | mA | VINx = VCC, DIS = GND; VDD=25V | 9 | |
| VDDx quiescent current | IVDDx | 2.7 | 4.4 | mA | VINx PWM at 0V to VCC at fSW = 500kHz, DIS = GND | 9 | |
| VCC UVLO rising threshold | VVCC_ON | 2.55 | 2.7 | 2.85 | V | 9 | |
| VCC UVLO falling threshold | VVCC_OFF | 2.35 | 2.5 | 2.65 | V | 9 | |
| VCC UVLO threshold hysteresis | VVCC_HYS | 0.2 | V | 9 | |||
| VCC UVLO ON delay | tVCC+ to OUT | 18 | 42 | 80 | µs | 9 | |
| VCC UVLO OFF delay | tVCC- to OUT | 0.5 | 1.2 | 7 | µs | 9 | |
| VCC UVLO deglitch filter | tVCCFIL | 0.4 | 0.9 | 3.1 | µs | 9 | |
| VDDx UVLO rising threshold | VVDD_ON | 7.7 | 8.5 | 8.9 | V | 8-V UVLO option | 9 |
| VDDx UVLO falling threshold | VVDD_OFF | 7.2 | 7.9 | 8.4 | V | 8-V UVLO option | 9 |
| VDDx UVLO threshold hysteresis | VVDD_HYS | 0.6 | V | 8-V UVLO option | 9 | ||
| VDDx UVLO OFF delay | tVDD- to OUT | 0.1 | 0.5 | 2 | µs | 9 | |
| VDDx UVLO ON delay | tVDD+ to OUT | 10 | µs | Features list gives 10µs maximum VDD power-up delay | 9 | ||
| Input high threshold voltage | VINx_H, VDIS_H | 2 | 2.3 | V | 9 | ||
| Input low threshold voltage | VINx_L, VDIS_L | 0.8 | 1 | V | 9 | ||
| Input threshold hysteresis | VINx_HYS, VDIS_HYS | 1 | V | 9 | |||
| INx pin pull-down resistance | RINxD | 50 | 90 | 185 | kΩ | INx = 3.3V | 9 |
| DIS pin pull-up resistance | RDISD | 50 | 90 | 185 | kΩ | DIS= 3.3V | 9 |
| Peak output source current | IO+ | -4 | A | CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz | 9 | ||
| Peak output sink current | IO- | 6 | A | CVDDx = 10 µF, CL = 0.22 µF, f = 1 kHz | 9 | ||
| Pull up resistance | ROH | 5 | Ω | IOUTx = -0.05A | 10 | ||
| Pull down resistance | ROL | 0.55 | Ω | IOUTx = 0.05A | 10 | ||
| Output active pull down on OUTx | VOUTPD | 1.6 | 2 | V | IOUT = 200mA, VDDx floating and unpowered. | 10 | |
| Dead time programming | DTS | -6 | 0.2 | 6 | ns | RDT=0~0.15kΩ | 10 |
| Dead time | DT | 86 | 99 | 112 | ns | RDT = 10 kΩ | 10 |
| Dead time | DT | 167 | 185 | 203 | ns | RDT = 20 kΩ | 10 |
| Dead time | DT | 399 | 443 | 487 | ns | RDT = 50 kΩ | 10 |
| Output rise time | tRISE | 8 | ns | CL=1.8nF, VDDx=12V, 20% to 80% | 10 | ||
| Output fall time | tFALL | 8 | ns | CL=1.8nF, VDDx=12V, 10% to 90% | 10 | ||
| Propagation delay low to high | tPDLH | 26 | 33 | 45 | ns | Input Pulse Width = 100ns, 500kHz, measure with Input VIH to output 10% | 10 |
| Propagation delay high to low | tPDHL | 26 | 33 | 45 | ns | Input Pulse Width = 100ns, 500kHz, measure with Input VIL to output 90% | 10 |
| DIS response delay high to low | tPD_DIS_HL | 27 | 48 | 80 | ns | tEN/DIS_FIL = 20 ns (typ), VDD=VDD_ON+0.2V and above, Input Pulse Width = 100ns, 500kHz | 10 |
| DIS response delay low to high | tPD_DIS_LH | 27 | 48 | 80 | ns | tEN/DIS_FIL = 20 ns (typ), VDD=VDD_ON+0.2V and above, Input Pulse Width = 100ns, 500kHz | 10 |
| Minimum input pulse width that passes to output | tPWmin | 4 | 12 | 30 | ns | VDD=VDD_ON+0.2V and above | 10 |
| Propagation delay matching | tDM | 0 | 6.5 | ns | Input Pulse Width = 100ns, 500kHz, TJ = -40°C to -10°C | 10 | |
| Propagation delay matching | tDM | 0 | 5 | ns | Input Pulse Width = 100ns, 500kHz, TJ = -10°C to +150°C | 10 | |
| Pulse width distortion | tPWD | 0 | 5 | ns | Input Pulse Width = 100ns, 500kHz | 10 | |
| High-level common mode transient immunity | /CMH/ | 125 | V/ns | VCM = 1500V | 10 | ||
| Low-level common mode transient immunity | /CML/ | 125 | V/ns | VCM = 1500V | 10 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | • Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority | 39 |
CAD (KiCad official)
- Symbol:
UCC21550BDWR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ucc21550bdwr-etched.step/ucc21550bdwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc21550bdwr.step/ucc21550bdwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
5f80a86ae72418d7, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).