component
MSP430F6747IPZR
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F6747IPZR
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)
MSP430F6747IPZR from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SD0P0 | input | SD24_B positive analog input for converter 0; short unused analog input pairs and connect them to analog ground. |
| 2 | SD0N0 | input | SD24_B negative analog input for converter 0; short unused analog input pairs and connect them to analog ground. |
| 3 | SD1P0 | input | SD24_B positive analog input for converter 1; short unused analog input pairs and connect them to analog ground. |
| 4 | SD1N0 | input | SD24_B negative analog input for converter 1; short unused analog input pairs and connect them to analog ground. |
| 5 | SD2P0 | input | SD24_B positive analog input for converter 2; short unused analog input pairs and connect them to analog ground. |
| 6 | SD2N0 | input | SD24_B negative analog input for converter 2; short unused analog input pairs and connect them to analog ground. |
| 7 | SD3P0 | input | SD24_B positive analog input for converter 3; short unused analog input pairs and connect them to analog ground. |
| 8 | SD3N0 | input | SD24_B negative analog input for converter 3; short unused analog input pairs and connect them to analog ground. |
| 9 | VASYS2 | power_out | Analog power supply selected between AVCC, AUXVCC1, AUXVCC2; connect the recommended capacitor CVSYS and tie externally to VASYS1. |
| 10 | AVSS2 | power_in | Analog ground supply. |
| 11 | VREF | power_in | SD24_B external reference voltage. |
| 12 | NC | unconnected | Not connected on MSP430F674x devices (SD4P0 on F677x/F676x). |
| 13 | NC | unconnected | Not connected on MSP430F674x devices (SD4N0 on F677x/F676x). |
| 14 | NC | unconnected | Not connected on MSP430F674x devices (SD5P0 on F677x/F676x). |
| 15 | NC | unconnected | Not connected on MSP430F674x devices (SD5N0 on F677x/F676x). |
| 16 | NC | unconnected | Not connected on MSP430F674x devices (SD6P0 on F677x). |
| 17 | NC | unconnected | Not connected on MSP430F674x devices (SD6N0 on F677x). |
| 18 | AVSS1 | power_in | Analog ground supply. |
| 19 | AVCC | power_in | Analog power supply. |
| 20 | VASYS1 | power_out | Analog power supply selected between AVCC, AUXVCC1, AUXVCC2; connect the recommended capacitor CVSYS and tie externally to VASYS2. |
| 21 | AUXVCC2 | power_in | Auxiliary power supply AUXVCC2. |
| 22 | AUXVCC1 | power_in | Auxiliary power supply AUXVCC1. |
| 23 | VDSYS1 | power_out | Digital power supply selected between DVCC, AUXVCC1, AUXVCC2; connect the recommended capacitor CVSYS and tie externally to VDSYS2. |
| 24 | DVCC | power_in | Digital power supply. |
| 25 | DVSS1 | power_in | Digital ground supply. |
| 26 | VCORE | power_in | Regulated core power supply for internal use only, no external current loading; connect only the recommended capacitor CVCORE (470 nF). |
| 27 | XIN | bidirectional | Input terminal for crystal oscillator. |
| 28 | XOUT | bidirectional | Output terminal for crystal oscillator. |
| 29 | AUXVCC3 | power_in | Auxiliary power supply AUXVCC3 for the backup subsystem. |
| 30 | RTCCAP1 | input | External time capture pin 1 for RTC_C. |
| 31 | RTCCAP0 | input | External time capture pin 0 for RTC_C. |
| 32 | P1.5/SMCLK/CB0/A5 | bidirectional | General-purpose digital I/O with port interrupt, SMCLK output, Comparator_B input CB0, or 10-bit ADC analog input A5. |
| 33 | P1.4/MCLK/CB1/A4 | bidirectional | General-purpose digital I/O with port interrupt, MCLK output, Comparator_B input CB1, or 10-bit ADC analog input A4. |
| 34 | P1.3/ADC10CLK/A3 | bidirectional | General-purpose digital I/O with port interrupt, ADC10_A clock output, or 10-bit ADC analog input A3. |
| 35 | P1.2/ACLK/A2 | bidirectional | General-purpose digital I/O with port interrupt, ACLK output, or 10-bit ADC analog input A2. |
| 36 | P1.1/TA2.1/CBOUT/VeREF+/A1 | bidirectional | General-purpose digital I/O with port interrupt, Timer TA2 CCR1, Comparator_B output, positive external ADC reference input, or analog input A1. |
| 37 | P1.0/TA1.1/VeREF-/A0 | bidirectional | General-purpose digital I/O with port interrupt, Timer TA1 CCR1, negative external ADC reference input, or analog input A0. |
| 38 | COM0 | bidirectional | LCD common output COM0 for LCD backplane. |
| 39 | COM1 | bidirectional | LCD common output COM1 for LCD backplane. |
| 40 | P1.6/COM2 | bidirectional | General-purpose digital I/O with port interrupt or LCD common output COM2. |
| 41 | P1.7/COM3 | bidirectional | General-purpose digital I/O with port interrupt or LCD common output COM3. |
| 42 | P2.0/PM_TA0.0/BSL_TX/COM4 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default Timer TA0 CCR0), bootloader data transmit, or LCD common COM4. |
| 43 | P2.1/PM_TA0.1/BSL_RX/COM5 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default Timer TA0 CCR1), bootloader data receive, or LCD common COM5. |
| 44 | P2.2/PM_TA0.2/COM6 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default Timer TA0 CCR2), or LCD common COM6. |
| 45 | P2.3/PM_TA1.0/COM7 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default Timer TA1 CCR0), or LCD common COM7. |
| 46 | LCDCAP/R33 | bidirectional | LCD capacitor connection and input/output of most positive analog LCD voltage (V1); must be connected to DVSS if not used. |
| 47 | P2.4/PM_TA2.0/R23 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default Timer TA2 CCR0), or second most positive analog LCD voltage (V2) port. |
| 48 | P2.5/PM_UCB0SOMI/PM_UCB0SCL/LCDREF/R13 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default eUSCI_B0 SOMI/I2C clock), external LCD reference input, or third most positive LCD voltage port R13. |
| 49 | P2.6/PM_UCB0SIMO/PM_UCB0SDA/R03 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default eUSCI_B0 SIMO/I2C data), or lowest analog LCD voltage (V5) port. |
| 50 | P2.7/PM_UCB0CLK/CB2 | bidirectional | General-purpose digital I/O with port interrupt and mappable function (default eUSCI_B0 clock), or Comparator_B input CB2. |
| 51 | P3.0/PM_UCA0RXD/PM_UCA0SOMI | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A0 UART receive / SPI SOMI). |
| 52 | P3.1/PM_UCA0TXD/PM_UCA0SIMO/S39 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A0 UART transmit / SPI SIMO), or LCD segment S39. |
| 53 | P3.2/PM_UCA0CLK/S38 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A0 clock), or LCD segment S38. |
| 54 | P3.3/PM_UCA1CLK/S37 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A1 clock), or LCD segment S37. |
| 55 | P3.4/PM_UCA1RXD/PM_UCA1SOMI/S36 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A1 UART receive / SPI SOMI), or LCD segment S36. |
| 56 | P3.5/PM_UCA1TXD/PM_UCA1SIMO/S35 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A1 UART transmit / SPI SIMO), or LCD segment S35. |
| 57 | P3.6/PM_UCA2RXD/PM_UCA2SOMI/S34 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A2 UART receive / SPI SOMI), or LCD segment S34. |
| 58 | P3.7/PM_UCA2TXD/PM_UCA2SIMO/S33 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A2 UART transmit / SPI SIMO), or LCD segment S33. |
| 59 | P4.0/PM_UCA2CLK/S32 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A2 clock), or LCD segment S32. |
| 60 | P4.1/PM_UCA3RXD/PM_UCA3SOMI/S31 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A3 UART receive / SPI SOMI), or LCD segment S31. |
| 61 | P4.2/PM_UCA3TXD/PM_UCA3SIMO/S30 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A3 UART transmit / SPI SIMO), or LCD segment S30. |
| 62 | P4.3/PM_UCA3CLK/S29 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_A3 clock), or LCD segment S29. |
| 63 | P4.4/PM_UCB1SOMI/PM_UCB1SCL/S28 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_B1 SOMI/I2C clock), or LCD segment S28. |
| 64 | P4.5/PM_UCB1SIMO/PM_UCB1SDA/S27 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_B1 SIMO/I2C data), or LCD segment S27. |
| 65 | P4.6/PM_UCB1CLK/S26 | bidirectional | General-purpose digital I/O with mappable function (default eUSCI_B1 clock), or LCD segment S26. |
| 66 | P4.7/PM_TA3.0/S25 | bidirectional | General-purpose digital I/O with mappable function (default Timer TA3 CCR0), or LCD segment S25. |
| 67 | P5.0/SDCLK/S24 | bidirectional | General-purpose digital I/O, SD24_B bit stream clock input/output, or LCD segment S24. |
| 68 | P5.1/SD0DIO/S23 | bidirectional | General-purpose digital I/O, SD24_B converter 0 bit stream data input/output, or LCD segment S23. |
| 69 | P5.2/SD1DIO/S22 | bidirectional | General-purpose digital I/O, SD24_B converter 1 bit stream data input/output, or LCD segment S22. |
| 70 | P5.3/SD2DIO/S21 | bidirectional | General-purpose digital I/O, SD24_B converter 2 bit stream data input/output, or LCD segment S21. |
| 71 | P5.4/SD3DIO/S20 | bidirectional | General-purpose digital I/O, SD24_B converter 3 bit stream data input/output, or LCD segment S20. |
| 72 | P5.5/S19 | bidirectional | General-purpose digital I/O or LCD segment S19 (SD4DIO not available on F674x). |
| 73 | P5.6/S18 | bidirectional | General-purpose digital I/O or LCD segment S18 (SD5DIO not available on F674x). |
| 74 | P5.7/S17 | bidirectional | General-purpose digital I/O or LCD segment S17 (SD6DIO not available on F674x). |
| 75 | VDSYS2 | power_in | Digital power supply for I/Os; must be connected externally to VDSYS1 for proper device operation. |
| 76 | DVSS2 | power_in | Digital ground supply. |
| 77 | P6.0/S16 | bidirectional | General-purpose digital I/O or LCD segment S16. |
| 78 | P6.1/S15 | bidirectional | General-purpose digital I/O or LCD segment S15. |
| 79 | P6.2/S14 | bidirectional | General-purpose digital I/O or LCD segment S14. |
| 80 | P6.3/S13 | bidirectional | General-purpose digital I/O or LCD segment S13. |
| 81 | P6.4/S12 | bidirectional | General-purpose digital I/O or LCD segment S12. |
| 82 | P6.5/S11 | bidirectional | General-purpose digital I/O or LCD segment S11. |
| 83 | P6.6/S10 | bidirectional | General-purpose digital I/O or LCD segment S10. |
| 84 | P6.7/S9 | bidirectional | General-purpose digital I/O or LCD segment S9. |
| 85 | P7.0/S8 | bidirectional | General-purpose digital I/O or LCD segment S8. |
| 86 | P7.1/S7 | bidirectional | General-purpose digital I/O or LCD segment S7. |
| 87 | P7.2/S6 | bidirectional | General-purpose digital I/O or LCD segment S6. |
| 88 | P7.3/S5 | bidirectional | General-purpose digital I/O or LCD segment S5. |
| 89 | P7.4/S4 | bidirectional | General-purpose digital I/O or LCD segment S4. |
| 90 | P7.5/S3 | bidirectional | General-purpose digital I/O or LCD segment S3. |
| 91 | P7.6/S2 | bidirectional | General-purpose digital I/O or LCD segment S2. |
| 92 | P7.7/S1 | bidirectional | General-purpose digital I/O or LCD segment S1. |
| 93 | P8.0/S0 | bidirectional | General-purpose digital I/O or LCD segment S0. |
| 94 | P8.1/TACLK/RTCCLK/CB3 | bidirectional | General-purpose digital I/O, Timer clock input TACLK for TA0-TA3, RTCCLK clock output, or Comparator_B input CB3. |
| 95 | TEST/SBWTCK | input | Test mode pin selecting digital I/O on JTAG pins; Spy-Bi-Wire input clock. |
| 96 | PJ.0/TDO | bidirectional | General-purpose digital I/O or JTAG test data output. |
| 97 | PJ.1/TDI/TCLK | bidirectional | General-purpose digital I/O or JTAG test data input / test clock input. |
| 98 | PJ.2/TMS | bidirectional | General-purpose digital I/O or JTAG test mode select. |
| 99 | PJ.3/TCK | bidirectional | General-purpose digital I/O or JTAG test clock. |
| 100 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input (internal pullup enabled by default when configured as reset), nonmaskable interrupt input, or Spy-Bi-Wire data input/output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | LQFP-100(14x14) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 100 |
CAD (KiCad official)
- Symbol:
MSP430F6747IPZR - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
msp430f6747ipzr-etched.step/msp430f6747ipzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f6747ipzr.step/msp430f6747ipzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (180 pp, sha256
9c56caf6d0342159, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).