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Contents

README

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74LVC240AT20-13

Diodes Incorporated · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

74LVC240AT20-13 from Diodes Incorporated, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output Enable 1 (active low); when low, the 1A inputs pass to the 1Y outputs, and when high, the 1Y outputs are in the high-impedance state.
2 1A1 input Data input 1A1 of the first 4-bit buffer, passing to output 1Y1 when 1OE is low.
3 2Y4 tri_state Data output 2Y4 of the second 4-bit buffer, three-state and high-impedance when 2OE is high.
4 1A2 input Data input 1A2 of the first 4-bit buffer, passing to output 1Y2 when 1OE is low.
5 2Y3 tri_state Data output 2Y3 of the second 4-bit buffer, three-state and high-impedance when 2OE is high.
6 1A3 input Data input 1A3 of the first 4-bit buffer, passing to output 1Y3 when 1OE is low.
7 2Y2 tri_state Data output 2Y2 of the second 4-bit buffer, three-state and high-impedance when 2OE is high.
8 1A4 input Data input 1A4 of the first 4-bit buffer, passing to output 1Y4 when 1OE is low.
9 2Y1 tri_state Data output 2Y1 of the second 4-bit buffer, three-state and high-impedance when 2OE is high.
10 GND power_in Ground reference pin.
11 2A1 input Data input 2A1 of the second 4-bit buffer, passing to output 2Y1 when 2OE is low.
12 1Y4 tri_state Data output 1Y4 of the first 4-bit buffer, three-state and high-impedance when 1OE is high.
13 2A2 input Data input 2A2 of the second 4-bit buffer, passing to output 2Y2 when 2OE is low.
14 1Y3 tri_state Data output 1Y3 of the first 4-bit buffer, three-state and high-impedance when 1OE is high.
15 2A3 input Data input 2A3 of the second 4-bit buffer, passing to output 2Y3 when 2OE is low.
16 1Y2 tri_state Data output 1Y2 of the first 4-bit buffer, three-state and high-impedance when 1OE is high.
17 2A4 input Data input 2A4 of the second 4-bit buffer, passing to output 2Y4 when 2OE is low.
18 1Y1 tri_state Data output 1Y1 of the first 4-bit buffer, three-state and high-impedance when 1OE is high.
19 2OE input Output Enable 2 (active low); when low, the 2A inputs pass to the 2Y outputs, and when high, the 2Y outputs are in the high-impedance state.
20 VCC power_in Supply voltage pin for the device.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (operating) VCC 1.65 3.6 V Operating 3
Data Retention Supply Voltage VCC 1.5 V Data Retention Only 3
Input Voltage VI 0 5.5 V 3
High-Level Output Current IOH -4 mA VCC = 1.65V 3
High-Level Output Current IOH -8 mA VCC = 2.3V 3
High-Level Output Current IOH -12 mA VCC = 2.7V 3
High-Level Output Current IOH -24 mA VCC = 3.0V 3
Low-Level Output Current IOL 4 mA VCC = 1.65V 3
Low-Level Output Current IOL 8 mA VCC = 2.3V 3
Low-Level Output Current IOL 12 mA VCC = 2.7V 3
Low-Level Output Current IOL 24 mA VCC = 3.0V 3
Input Transition Rise or Fall Rate Δt/ΔV 10 ns/V 3
Operating Free-Air Temperature TA -40 125 °C 3
VCC Supply Voltage Range VCC -0.5 7 V 3
Input Voltage Range VI -0.5 7 V 3
Input Clamp Current IIK -20 mA VI < 0V 3
Output Clamp Current IOK -50 mA VO < 0V 3
Continuous Output Current IO -50 50 mA -0.5V < VO Vcc + 0.5V 3
Continuous Current through VCC ICC 100 mA 3
Continuous Current through GND IGND -100 mA 3
Operating Junction Temperature TJ -40 150 °C 3
Storage Temperature TSTG -65 150 °C 3
Total Power Dissipation PTOT 500 mW 3
High-Level Input Voltage VIH 1.7 V VCC 2.3V to 2.7V, TA = -40°C to +125°C 4
High-Level Input Voltage VIH 2 V VCC 3.0V to 3.6V, TA = -40°C to +125°C 4
Low-Level Input Voltage VIL 0.7 V VCC 2.3V to 2.7V, TA = -40°C to +125°C 4
Low-Level Input Voltage VIL 0.8 V VCC 3.0V to 3.6V, TA = -40°C to +125°C 4
High-Level Output Voltage VOH 1.05 V IOH = -4 mA, VCC 1.65V, TA = -40°C to +125°C 4
High-Level Output Voltage VOH 1.65 V IOH = -8 mA, VCC 2.3V, TA = -40°C to +125°C 4
High-Level Output Voltage VOH 2.05 V IOH = -12 mA, VCC 2.7V, TA = -40°C to +125°C 4
High-Level Output Voltage VOH 2.48 V IOH = -12 mA, VCC 3.0V, TA = -40°C to +125°C 4
High-Level Output Voltage VOH 2 V IOH = -24 mA, VCC 3.0V, TA = -40°C to +125°C 4
Low-Level Output Voltage VOL 0.3 V IOL = 100 μA, VCC 1.65V to 3.6V, TA = -40°C to +125°C 4
Low-Level Output Voltage VOL 0.65 V IOL = 4 mA, VCC 1.65V, TA = -40°C to +125°C 4
Low-Level Output Voltage VOL 0.8 V IOL = 8 mA, VCC 2.3V, TA = -40°C to +125°C 4
Low-Level Output Voltage VOL 0.6 V IOL = 12 mA, VCC 2.7V, TA = -40°C to +125°C 4
Power Down Leakage Current IOFF -20 20 μA VI or VO = 0 or 5.5V, VCC 0V, TA = -40°C to +125°C 4
Input Current, Control Pins II -20 20 μA VI = GND or 5.5V, VCC 0 to 3.6V, TA = -40°C to +125°C 4
Z-state Current, I/O Pins IOZ -20 20 uA VI = GND or 5.5V, VO = 0 to 5.5V, VCC 3.6V, TA = -40°C to +125°C 4
Supply Current ICC 40 μA VI = GND or VCC, IO = 0, VCC 3.6V, TA = -40°C to +125°C 4
Additional Supply Current ΔICC 5000 μA One input at VCC-0.6V, IO = 0A, VCC 2.7V to 3.6V, TA = -40°C to +125°C 4
Propagation Delay AN to YN tPD 1 16.9 ns VCC 1.8V ± 0.15V, Figure 1, TA = -40°C to +125°C 4
Propagation Delay AN to YN tPD 1 8.9 ns VCC 2.5V ± 0.2V, Figure 1, TA = -40°C to +125°C 4
Propagation Delay AN to YN tPD 1 9 ns VCC 2.7V, Figure 1, TA = -40°C to +125°C 4
Propagation Delay AN to YN tPD 1.5 8.3 ns VCC 3.3V ± 0.3V, Figure 1, TA = -40°C to +125°C 4
Enable Time OE to YN tEN 1 22.5 ns VCC 1.8V ± 0.15V, Figure 1, TA = -40°C to +125°C 4
Enable Time OE to YN tEN 1 12.4 ns VCC 2.5V ± 0.2V, Figure 1, TA = -40°C to +125°C 4
Enable Time OE to YN tEN 1 11 ns VCC 2.7V, Figure 1, TA = -40°C to +125°C 4
Enable Time OE to YN tEN 1.5 9 ns VCC 3.3V ± 0.3V, Figure 1, TA = -40°C to +125°C 4
Disable Time OE to YN tDIS 1 18.2 ns VCC 1.8V ± 0.15V, Figure 1, TA = -40°C to +125°C 4
Disable Time OE to YN tDIS 1 10.7 ns VCC 2.5V ± 0.2V, Figure 1, TA = -40°C to +125°C 4
Disable Time OE to YN tDIS 1 10 ns VCC 2.7V, Figure 1, TA = -40°C to +125°C 4
Disable Time OE to YN tDIS 1.7 9 ns VCC 3.3V ± 0.3V, Figure 1, TA = -40°C to +125°C 4
Output Skew Time tsk(0) 1.5 ns VCC 3.3V ± 0.3V, TA = -40°C to +125°C 4
Thermal Resistance Junction-to-Ambient θJA 74 °C/W TSSOP-20, 4-layer FR-4 board per JESD 51-7 (Note 9) 5
Thermal Resistance Junction-to-Case θJC 15 °C/W TSSOP-20, 4-layer FR-4 board per JESD 51-7 (Note 9) 5

CAD (KiCad official)

  • Symbol: 74LVC240AT20-13
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lvc240at20-13-etched.step / 74lvc240at20-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lvc240at20-13.step / 74lvc240at20-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (10 pp, sha256 337547a85943dc13, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF