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AD7665ASTZ

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Analog Devices Pre-ordered Chips, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

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AD7665ASTZ

Analog Devices · Pre-ordered Chips · LQFP-48(7x7)

AD7665ASTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog power ground pin that must be tied to analog ground.
2 AVDD power_in Input analog power pin, nominally 5 V.
3 NC unconnected No connect.
4 BYTESWAP input Parallel mode 8/16-bit selection: LOW puts the LSB on D[7:0] and the MSB on D[15:8], HIGH swaps them.
5 OB/2C input Output coding select: HIGH gives straight binary output, LOW gives twos complement output with the MSB inverted.
6 WARP input Mode select: when HIGH and IMPULSE LOW, selects the fastest mode, which requires a minimum conversion rate to guarantee full accuracy.
7 IMPULSE input Mode select: when HIGH and WARP LOW, selects a reduced power mode where power dissipation is approximately proportional to sampling rate.
8 SER/PAR input Serial/parallel select: LOW selects the parallel port, HIGH selects the serial interface mode.
9 D0 output Parallel port data output bit 0; high impedance when SER/PAR is HIGH.
10 D1 output Parallel port data output bit 1; high impedance when SER/PAR is HIGH.
11 D2/DIVSCLK[0] bidirectional Parallel port data bit 2 when SER/PAR is LOW; in serial master read-after-convert mode it is the DIVSCLK[0] serial clock slow-down input.
12 D3/DIVSCLK[1] bidirectional Parallel port data bit 3 when SER/PAR is LOW; in serial master read-after-convert mode it is the DIVSCLK[1] serial clock slow-down input.
13 D4/EXT/INT bidirectional Parallel port data bit 4 when SER/PAR is LOW; in serial mode it selects the internal (LOW) or external (HIGH) data clock.
14 D5/INVSYNC bidirectional Parallel port data bit 5 when SER/PAR is LOW; in serial mode it selects the active state of SYNC.
15 D6/INVSCLK bidirectional Parallel port data bit 6 when SER/PAR is LOW; in serial mode it inverts the SCLK signal.
16 D7/RDC/SDIN bidirectional Parallel port data bit 7 when SER/PAR is LOW; in serial mode it is an external data input for daisy-chain or the read mode select.
17 OGND power_in Input/output interface digital power ground, connected to the digital system ground.
18 OVDD power_in Input/output interface digital power, nominally at the host interface supply of 5 V or 3 V.
19 DVDD power_in Digital power pin, nominally 5 V.
20 DGND power_in Digital power ground pin.
21 D8/SDOUT bidirectional Parallel port data bit 8 when SER/PAR is LOW; in serial mode it is the serial data output synchronized to SCLK.
22 D9/SCLK bidirectional Parallel port data bit 9 when SER/PAR is LOW; in serial mode it is the serial data clock input or output.
23 D10/SYNC bidirectional Parallel port data bit 10 when SER/PAR is LOW; in serial mode it is the digital output frame synchronization signal.
24 D11/RDERROR bidirectional Parallel port data bit 11 when SER/PAR is LOW; in serial slave mode it is the incomplete read error flag.
25 D12 output Parallel port data output bit 12; high impedance when SER/PAR is HIGH.
26 D13 output Parallel port data output bit 13; high impedance when SER/PAR is HIGH.
27 D14 output Parallel port data output bit 14; high impedance when SER/PAR is HIGH.
28 D15 output Parallel port data output bit 15; high impedance when SER/PAR is HIGH.
29 BUSY output Busy output that goes HIGH when a conversion starts and LOW when it completes and data is latched; its falling edge can clock data ready.
30 DGND power_in Must be tied to digital ground.
31 RD input Read data input; when CS and RD are both LOW the interface output bus is enabled.
32 CS input Chip select; when CS and RD are both LOW the interface output bus is enabled, and CS also gates the external serial clock.
33 RESET input Reset input; a HIGH level resets the AD7665 and aborts any current conversion, and it may be tied to DGND if unused.
34 PD input Power-down input; a HIGH level reduces power consumption and inhibits conversions after the current one completes.
35 CNVST input Start conversion; a falling edge puts the sample-and-hold into hold and initiates a conversion.
36 AGND power_in Must be tied to analog ground.
37 REF input Reference input voltage.
38 REFGND passive Reference input analog ground, which should be a low impedance return to the reference.
39 INGND passive Analog input ground used to sense the analog input signal.
40 INA passive Analog input A; input range is configured per Table I.
41 INB passive Analog input B; input range is configured per Table I.
42 INC passive Analog input C; input range is configured per Table I.
43 IND passive Analog input D; input range is configured per Table I.
44 NC unconnected No connect.
45 NC unconnected No connect.
46 NC unconnected No connect.
47 NC unconnected No connect.
48 NC unconnected No connect.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-48(7x7)
Category Interface ICs
Pins 48

CAD (KiCad official)

  • Symbol: AD7665ASTZ
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad7665astz-etched.step / ad7665astz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7665astz.step / ad7665astz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (23 pp, sha256 7be5be03027f1864, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF