CD5026ITS from Shenzhen CYT Semicon Tech, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Voltage input pin with an operating input range of 13V to 100V; supplies outside this range need an external regulator.
2	UVLO	input	Undervoltage lockout pin set by an external divider; the VCC and REF regulators are enabled at 0.4V and the SS pin is released at 1.25V.
3	CS	input	Current-sense pin for current-mode control and limiting; output pulses terminate and enter cycle-by-cycle current limit when CS exceeds 0.5V.
4	RES	passive	Restart timer pin; when the RES capacitor reaches 2.5V the soft-start capacitor is fully discharged and then released with a 1µA pull-up.
5	TIME	input	Gate-driver overlap or dead-time control pin; RSET between TIME and AGND sets in-phase overlap, and RSET between TIME and REF sets anti-phase dead time.
6	REF	power_out	5V reference voltage output with a maximum output current of 10 mA, requiring a 0.1µF decoupling capacitor to ground.
7	VCC	power_out	High-voltage start-up regulator output with a regulation range of 7.3V to 7.9V, which an auxiliary winding can raise above the setpoint to switch the start-up regulator off.
8	OUT_A	output	Main switch PWM gate driver output capable of 3A peak sink current.
9	OUT_B	output	Active-clamp switch gate driver output capable of 0.5A peak source and sink current.
10	PGND	power_in	Power ground, connected to signal ground at a single point.
11	AGND	power_in	Signal ground, connected to power ground at a single point.
12	SS	passive	Soft-start pin; an external capacitor and the internal 50µA current source set the soft-start ramp, and the SS current drops to 1µA after restart.
13	COMP	input	PWM control pin fed through the optocoupler into an internal NPN current mirror; PWM duty cycle is maximum when input current is zero.
14	RT	passive	Oscillator frequency control pin, normally biased at 2V; the total external resistance between RT and AGND sets the internal oscillator frequency.
15	SYNC	bidirectional	Oscillator synchronization input/output that lets the internal oscillator lock to an external clock or to other CD5026 devices.
16	DCL	input	Maximum duty-cycle control pin; a resistor divider from RT to AGND sets the maximum OUT_A duty cycle.

Key specifications

Parameter	Value
Manufacturer	Shenzhen CYT Semicon Tech
Package	TSSOP-16
Category	Power Management
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VIN to GND voltage	VIN	-0.3		105	V		3
VCC to GND voltage	VCC	-0.3		16	V		3
CS to GND voltage	CS	-0.3		1	V		3
COMP input current		0		10	mA		3
ALL other pin to GND voltage		-0.3		7	V		3
Input voltage (recommended)		13		100	V		3
VCC voltage (recommended)		8		15	V		3
Operating temperature range		-40		125	℃		3
VCC regulated output voltage	VCCReg	7.3	7.6	7.9	V		4
VCC load capability	IVCC-limit	20	25		mA		4
Startup regulator leakage current	IVIN		165	500	μA	UVLO=0.6V	4
Shutdown current (UVLO off)	IIN		350	450	μA	UVLO=0V	4
VCC undervoltage hysteresis		1	1.5	2	V		4
VCC supply current	ICC			4.2	mA	UVLO=1.5V	4
Reference voltage	VRef	4.85	5	5.15	V	IREF=0mA	4
Reference adjustment range	DRef		25	50	mV	IREF=0mA~10mA	4
Reference current range	IRef	10	20		mA	UVLO=1.5V	4
UVLO undervoltage shutdown	Vstd	0.3	0.4	0.5	V		4
UVLO reference voltage	VUVLO	1.21	1.25	1.29	V	DCL=6.5V	4
UVLO hysteresis current	IUVLO	16	20	24	μA	UVLO=1.5V	4
Cycle-by-cycle current limit threshold	VCS	0.45	0.5	0.55	V		4
Leading edge blanking time	tLEB	70	100	130	ns		4
CS pull-down resistance	RSCS		30	65	Ω		4
Restart threshold voltage	VOCR	2.4	2.55	2.7	V	UVLO=1.5V	4
Overcurrent protection charge current	IOSC	7.5	10	12.5	μA		4
Overcurrent protection discharge current		7.5	10	12.5	μA		4
Soft-start charge current	ISS	38	50	58	μA	UVLO=1.5V	5
Soft-start sink current		38	50	58			5
Soft-start current source after restart		0.6	1	1.3	μA		5
Pulse frequency 1	FOSC1	180	200	220	kHz	RT=30kΩ	5
Pulse frequency 2	FOSC2	520	590	660	kHz	RT=10kΩ	5
Minimum output duty cycle	Duty(min)			0	%	ICOMP=1mA	5
Slope compensation amplitude		75	90	115	mV	PWM比较器到CS的增量	5
OUT-A output high saturation	VAouth		0.05	0.1	V	MOS管驱动，IOUT=-10mA	5
OUT-A output low saturation	VAoutl		0.06	0.9	V	MOS管驱动，IOUT=10mA	5
OUT-B output high saturation	VBouth		0.1	0.2	V	IOUT=-10mA	5
OUT-B output low saturation	VBoutl		0.1	0.2	V	IOUT=10mA	5
Overlap time		70	100	130	ns	RSET=34.8kΩ连接至GND，重叠50％至50％	6
Dead time		70	100	130	ns	RSET=30kΩ连接至REF，重叠50％至50％	6
Over-temperature protection point	TSD	150	165		℃		6
UVLO hysteresis			0.1		V		4
Overcurrent to output delay	tLIM_DLY		40		ns	CS从0到0.6 V步进，至OUT端输出的90％，CGATE=0nF	4
Output delay to OUT-A low	tOUT_DLY		40		ns	COMP 为 2V，当 CS 由 0 升至 0.4V	5
Maximum output duty cycle 1	Duty(max1)		80		%	UVLO=1.3V，COMP=open，VDCL=2.5V	5
Maximum output duty cycle 2	Duty(max2)		70		%	UVLO=1.3V，COMP=open，VDCL=VRT*0.875	5
Maximum output duty cycle 3	Duty(max3)		40		%	UVLO=2.92V，COMP=open，VDCL=2.5V	5
SS pin to PWM bias voltage			1.4		V		5
COMP input impedance			1700		Ω		5
OUT-A rise time	tra		20		ns	CGATE=2.2nF	5
OUT-A fall time	tfa		15		ns	CGATE=2.2nF	5
OUT-B rise time	trb		15		ns	CGATE=470pF	5
OUT-B fall time	tfb		15		ns	CGATE=470pF	5
Over-temperature protection hysteresis			25		℃		6

CAD (KiCad official)

Symbol: CD5026ITS
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: cd5026its-etched.step / cd5026its-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd5026its.step / cd5026its.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Shenzhen CYT Semicon Tech datasheet (14 pp, sha256 2740d483b74f75a9, retrieved 2026-11-04, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CD5026ITS

Verified CD5026ITS

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README