component
IRS2103STRPBF
Public Made by Adomby adom
Infineon Technologies Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownIRS2103STRPBF
Infineon Technologies · Gate Drive ICs · SOIC-8
IRS2103STRPBF from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Low-side and logic fixed supply, operated from 10 V to 20 V with an absolute maximum of -0.3 V to 25 V referenced to COM. |
| 2 | HIN | input | Logic input for the high-side gate driver output (HO), in phase, with a logic input voltage range of -0.3 V to VCC + 0.3 V and compatibility down to 3.3 V logic. |
| 3 | LIN | input | Logic input for the low-side gate driver output (LO), out of phase, with a logic input voltage range of -0.3 V to VCC + 0.3 V and compatibility down to 3.3 V logic. |
| 4 | COM | power_in | Low-side return and the reference for all voltage parameters in the absolute maximum ratings. |
| 5 | LO | output | Low-side gate drive output, swinging between 0 V and VCC. |
| 6 | VS | power_in | High-side floating supply return, with a supply offset of 600 V maximum in recommended operation and logic operational for VS from -5 V to +600 V. |
| 7 | HO | output | High-side gate drive output, swinging between VS and VB. |
| 8 | VB | power_in | High-side floating supply, recommended at VS + 10 V to VS + 20 V with an absolute maximum of 625 V referenced to COM. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side floating absolute voltage | VB | -0.3 | 625 | V | 2 | ||
| Low-side and logic fixed supply voltage | VCC | -0.3 | 25 | V | 2 | ||
| Allowable offset supply voltage transient | dVs/dt | 50 | V/ns | 2 | |||
| Package power dissipation @ TA ≤ +25 °C | PD | 0.625 | W | 8 Lead SOIC, TA ≤ +25 °C | 2 | ||
| Thermal resistance, junction to ambient | RthJA | 200 | °C/W | 8 Lead SOIC | 2 | ||
| Junction temperature | TJ | 150 | °C | 2 | |||
| Storage temperature | TS | -55 | 150 | °C | 2 | ||
| Lead temperature (soldering) | TL | 300 | °C | soldering, 10 seconds | 2 | ||
| High-side floating supply offset voltage | VS | 600 | V | Note 1 | 2 | ||
| Low-side and logic fixed supply voltage | VCC | 10 | 20 | V | 2 | ||
| Low-side output voltage | VLO | 0 | V | 2 | |||
| Logic input voltage (HIN & LIN) | VIN | 0 | V | 2 | |||
| Ambient temperature | TA | -40 | 125 | °C | 2 | ||
| Logic '1' (HIN) & Logic '0' (LIN) input voltage | VIH | 2.5 | V | 3 | |||
| Logic '0' (HIN) & Logic '1' (LIN) input voltage | VIL | 0.8 | V | 3 | |||
| High level output voltage, VBIAS - VO | VOH | 0.05 | 0.2 | V | 3 | ||
| Low level output voltage, VO | VOL | 0.02 | 0.1 | V | 3 | ||
| Offset supply leakage current | ILK | 50 | µA | VB = VS = 600 V | 3 | ||
| Quiescent VBS supply current | IQBS | 30 | 55 | µA | 3 | ||
| Quiescent VCC supply current | IQCC | 150 | 270 | µA | 3 | ||
| Logic '1' input bias current | IIN+ | 3 | 10 | µA | HIN = 5 V, LIN = 0 V | 3 | |
| Logic '0' input bias current | IIN- | 5 | µA | HIN = 0 V, LIN = 5 V | 3 | ||
| VCC supply undervoltage positive going threshold | VCCUV+ | 8 | 8.9 | 9.8 | V | 3 | |
| VCC supply undervoltage negative going threshold | VCCUV- | 7.4 | 8.2 | 9 | V | 3 | |
| Output high short circuit pulsed current | IO+ | 130 | 290 | mA | VO = 0 V, VIN = VIH, PW ≤ 10 µs | 3 | |
| Output low short circuit pulsed current | IO- | 270 | 600 | mA | VO = 15 V, VIN = VIL, PW ≤ 10 µs | 3 | |
| Turn-on propagation delay | ton | 680 | 820 | ns | VS = 0 V | 3 | |
| Turn-off propagation delay | toff | 150 | 220 | ns | VS = 600 V | 3 | |
| Turn-on rise time | tr | 70 | 170 | ns | 3 | ||
| Turn-off fall time | tf | 35 | 90 | ns | 3 | ||
| Deadtime, LS turn-off to HS turn-on | DT | 400 | 520 | 650 | ns | HS turn-on to LS turn-off | 3 |
| Delay matching, HS & LS turn-on/off | MT | 60 | ns | 3 |
CAD (KiCad official)
- Symbol:
IRS2103STRPBF - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
irs2103strpbf-etched.step/irs2103strpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);irs2103strpbf.step/irs2103strpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (14 pp, sha256
fb76ff8fcd7f1350, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).