FT602Q-B-T from FTDI, in a QFN-76(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Ground.
2	AVDD	power_in	+1.0V power input for the PLL (0.9 to 1.1V operating, can be fed from DV10).
3	VD10	power_in	+1.0V core voltage input.
4	BE_0	bidirectional	Parallel FIFO bus byte enable I/O bit 0.
5	BE_1	bidirectional	Parallel FIFO bus byte enable I/O bit 1.
6	BE_2	bidirectional	Parallel FIFO bus byte enable I/O bit 2.
7	BE_3	bidirectional	Parallel FIFO bus byte enable I/O bit 3.
8	TXE_N	output	In 245 Synchronous FIFO mode, transmit FIFO empty output (write only when logic 0); in Multi-Channel FIFO mode, optional Status Valid output.
9	RXF_N	output	In 245 Synchronous FIFO mode add external pull up in normal operation; in Multi-Channel FIFO mode, Data Receive Acknowledge output.
10	RESERVED1	input	Reserved; add external pull up in normal operation.
11	WR_N	input	Active-low Write Enable input in 245 Synchronous FIFO mode; Data Transaction Request input in Multi-Channel FIFO mode.
12	RESERVED2	input	Add external pull up in normal operation.
13	RESERVED3	input	Add external pull up in normal operation.
14	VCCIO	power_in	Power input for the I/O block, supports +2.5/+3.3V.
15	RESET_N	input	Chip reset input, active low.
16	INT_N	input	Interrupt input, active low; used for I2C interrupt request or to wake the device from sleep.
17	SCL	bidirectional	I2C serial clock line (open drain).
18	SDA	bidirectional	I2C serial data line (open drain).
19	RESERVED4	unconnected	Reserved; do not connect.
20	VCC33	power_in	+3.3V power input for chip and internal LDO.
21	XI	input	Crystal input for the internal oscillator (30MHz crystal recommended).
22	XO	output	Crystal output for the internal oscillator.
23	DP	bidirectional	Hi-speed USB differential transceiver (positive).
24	VCC33	power_in	+3.3V power input for chip and internal LDO.
25	DM	bidirectional	Hi-speed USB differential transceiver (negative).
26	GND	power_in	Ground.
27	RREF	passive	PHY reference resistor pin; connect a 1.6k ohm 1% resistor to ground to provide reference voltage to the USB2 PHY.
28	VDDA	power_in	+3.3V power input for the USB2.0 and USB3.0 PHYs.
29	GND	power_in	Ground.
30	VD10	power_in	+1.0V core voltage input.
31	TODN	output	Super Speed USB transmitter differential pair (negative).
32	TODP	output	Super Speed USB transmitter differential pair (positive).
33	VD10	power_in	+1.0V core voltage input.
34	RIDN	input	Super Speed USB receiver differential pair (negative).
35	RIDP	input	Super Speed USB receiver differential pair (positive).
36	GND	power_in	Ground.
37	VBUS	power_in	USB bus power detect pin; input voltage should be greater than 2.7V.
38	VCC33	power_in	+3.3V power input for chip and internal LDO.
39	DV10	power_out	+1.0V output from internal LDO; connect to VD10 and AVDD with a 4.7uF capacitor to ground recommended.
40	DATA_0	input	Parallel FIFO bus data input bit 0.
41	DATA_1	input	Parallel FIFO bus data input bit 1.
42	DATA_2	input	Parallel FIFO bus data input bit 2.
43	DATA_3	input	Parallel FIFO bus data input bit 3.
44	DATA_4	input	Parallel FIFO bus data input bit 4.
45	DATA_5	input	Parallel FIFO bus data input bit 5.
46	DATA_6	input	Parallel FIFO bus data input bit 6.
47	DATA_7	input	Parallel FIFO bus data input bit 7.
48	VD10	power_in	+1.0V core voltage input.
49	VCCIO	power_in	Power input for the I/O block, supports +2.5/+3.3V.
50	DATA_8	bidirectional	Parallel FIFO bus data I/O bit 8.
51	DATA_9	bidirectional	Parallel FIFO bus data I/O bit 9.
52	DATA_10	bidirectional	Parallel FIFO bus data I/O bit 10.
53	DATA_11	bidirectional	Parallel FIFO bus data I/O bit 11.
54	DATA_12	bidirectional	Parallel FIFO bus data I/O bit 12.
55	DATA_13	bidirectional	Parallel FIFO bus data I/O bit 13.
56	DATA_14	bidirectional	Parallel FIFO bus data I/O bit 14.
57	DATA_15	bidirectional	Parallel FIFO bus data I/O bit 15.
58	CLK	output	Parallel FIFO bus clock output to the FIFO bus master, configurable as 66MHz or 100MHz for both FIFO bus modes.
59	VCCIO	power_in	Power input for the I/O block, supports +2.5/+3.3V.
60	DATA_16	input	Parallel FIFO bus data input bit 16.
61	DATA_17	input	Parallel FIFO bus data input bit 17.
62	DATA_18	input	Parallel FIFO bus data input bit 18.
63	DATA_19	input	Parallel FIFO bus data input bit 19.
64	DATA_20	input	Parallel FIFO bus data input bit 20.
65	DATA_21	input	Parallel FIFO bus data input bit 21.
66	DATA_22	input	Parallel FIFO bus data input bit 22.
67	DATA_23	input	Parallel FIFO bus data input bit 23.
68	VCCIO	power_in	Power input for the I/O block, supports +2.5/+3.3V.
69	DATA_24	input	Parallel FIFO bus data input bit 24.
70	DATA_25	input	Parallel FIFO bus data input bit 25.
71	DATA_26	input	Parallel FIFO bus data input bit 26.
72	DATA_27	input	Parallel FIFO bus data input bit 27.
73	DATA_28	input	Parallel FIFO bus data input bit 28.
74	DATA_29	input	Parallel FIFO bus data input bit 29.
75	DATA_30	input	Parallel FIFO bus data input bit 30.
76	DATA_31	input	Parallel FIFO bus data input bit 31.
77	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	FTDI
Package	QFN-76(9x9)
Category	Communication Interface Chip/UART/485/232
Pins	77

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage Temperature		-65		150	°C		15
Ambient Operating Temperature (Power Applied)		-40		85	°C		15
VCC33/VDDA Supply Voltage	VCC33/VDDA	-0.3		4.6	V		15
VCCIO Supply Voltage	VCCIO	-0.3		4	V		15
VD10 Core Supply Voltage	VD10	-0.5		1.4	V		15
AVDD PLL Supply Voltage	AVDD	-0.5		1.4	V		15
IOs DC Input Voltage		-0.5			V	-0.5 to +VCCIO+0.5 V	15
VCC Operating Supply Voltage	VCC33/VDDA	3	3.3	3.6	V		16
VCCIO Operating Supply Voltage	VCCIO_1	3	3.3	3.6	V	VCCIO=3.3V	16
VCCIO Operating Supply Voltage	VCCIO_2	2.3	2.5	2.7	V	VCCIO=2.5V	16
VCCIO Operating Supply Voltage	VCCIO_3	1.65	1.8	1.95	V	VCCIO=1.8V	16
Core/PLL Operating Supply Voltage	VD10/AVDD	0.9	1	1.1	V		16
VCCIO Operating Supply Voltage 3.3V	VCCIO_3.3V	3	3.3	3.6	V	Normal Operation	17
VCCIO Operating Supply Voltage 2.5V	VCCIO_2.5V	2.3	2.5	2.7	V	Normal Operation	17
VCCIO Operating Supply Voltage 1.8V	VCCIO_1.8V	1.65	1.8	1.95	V	Normal Operation	17
Input high voltage	VIH	0.7			xVCCIO	Normal Operation; printed VCCIO*0.7	17
Input/output Leakage	Iin/Iout(3.3V)	-10		10	uA	Without pull-up/down	17
Input pull-up/pull down resistance	Rpu/Rpd	30	50	75	KΩ	Vout=0~VCCIO	17
Output drive strength	Iout(VCCIO=3.3V)	10			mA	Total current	17
Output drive strength	Iout(VCCIO=2.5V)	9.4			mA	Total current	17
Pin Capacitance	Cp			2	pF		17
Slave Drive Data Set Up Time	T1	3			ns		14
Slave Drive Data Hold Time	T2	3.5			ns		14
Master Drive Data Set Up Time	T3	1			ns		14
Master Drive Date Hold Time	T4	4.8			ns		14
VCC Operating Supply Current	Icc_1		85		mA	Idle, SuperSpeed	16
VCC Operating Supply Current	Icc_2		69		mA	Idle, High Speed	16
VCC Operating Supply Current	Icc_3		185		mA	FHD 1080P@60fps Output	16
VCC Operating Supply Current	Icc_3		4		mA	USB Suspend	16
VCCIO Operating Supply Current	Iccio_1		4.5		mA	No data transfer	16
VCCIO Operating Supply Current	Iccio_2		9.5		mA	Data transfer	16
VCCIO Operating Supply Current	Iccio_3		70		μA	USB Suspend	16
ESD HBM			2		kV	JEDEC EIA/JESD22-A114-B, Class 2; printed ±2kV	15
ESD MM			200		V	JEDEC EIA/JESD22-A115-A, Class B; printed ±200V	15
ESD CDM			500		V	JEDEC EIA/JESD22-C101-D, Class-III; printed ±500V	15
Latch-up			200		mA	JESD78, Trigger Class-II; printed ±200mA	15

CAD (KiCad official)

Symbol: FT602Q-B-T
Footprint: Package_DFN_QFN:QFN-76-1EP_9x9mm_P0.4mm_EP3.8x3.8mm
3D model: QFN-76(9x9) (KiCad packages3D, STEP)
3D model files: ft602q-b-t-etched.step / ft602q-b-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft602q-b-t.step / ft602q-b-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: FTDI datasheet (28 pp, sha256 1f49dbe70a6ac962, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

FT602Q-B-T

Verified FT602Q-B-T

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README