component
2DIB1411FXUMA1
Public Made by Adomby adom
Infineon Technologies Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown2DIB1411FXUMA1
Infineon Technologies · Digital Isolators · SOIC-8
2DIB1411FXUMA1 from Infineon Technologies, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Positive supply voltage 1 (side 1 supply; operating supply range 2.7 V to 6.5 V). |
| 2 | OUTA | output | Channel A output (1+1 configuration; fail-safe default output high for 2DIB1411F when input side is unpowered). |
| 3 | INB | input | Channel B input with fixed TTL input threshold. |
| 4 | GND1 | power_in | Ground 1, reference for side 1 supply. |
| 5 | GND2 | power_in | Ground 2, reference for side 2 supply. |
| 6 | OUTB | output | Channel B output (1+1 configuration; default output high for 2DIB1411F when input side is unpowered). |
| 7 | INA | input | Channel A input with fixed TTL input threshold. |
| 8 | VDD2 | power_in | Positive supply voltage 2 (side 2 supply; operating supply range 2.7 V to 6.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD1, VDD2 | -0.5 | 7.5 | V | 13 | ||
| Voltage at pins INx | VINX | -0.5 | V | max printed as VDDI + 0.5 | 13 | ||
| Voltage at pins OUTx | VOUTX | -0.5 | V | max printed as VDDO + 0.5 | 13 | ||
| Average output current per pin | IOUT | -10 | 10 | mA | 13 | ||
| Junction temperature | TJ | -40 | 150 | °C | 13 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 13 | ||
| Soldering temperature | TSOL | 260 | °C | reflow / wave soldering, according to JESD22A111 | 13 | ||
| Electrostatic discharge HBM | VESD_HBM | 2 | kV | Human body model (HBM) according to JESD22-A114-B | 13 | ||
| Electrostatic discharge CDM | VESD_CDM | 500 | V | Charged-device model (CDM) according to JESD22-002 | 13 | ||
| Latch-up immunity | ILU | 150 | mA | JEDEC78E Class II, pin voltages according to abs. max. ratings | 13 | ||
| Data rate | DR | 0 | 40 | Mbps | 16 | ||
| Supply voltage | VDD1, VDD2 | 2.7 | 6.5 | V | 16 | ||
| High-level input voltage (TTL) | VIH | 2 | V | max printed as VDDI | 16 | ||
| Low-level input voltage (TTL) | VIL | 0 | 0.8 | V | 16 | ||
| Ambient temperature | TA | -40 | 125 | °C | 16 | ||
| Static common-mode transient immunity | /CMH/ | 100 | kV/µs | VCM = 1500 V; VINX tied to VDDI | 16 | ||
| Supply UVLO turn-on threshold | VDDX(UVLOon) | 2.42 | 2.55 | 2.68 | V | 16 | |
| Supply UVLO turn-off threshold | VDDX(UVLOoff) | 2.35 | 2.45 | 2.55 | V | 16 | |
| Supply UVLO hysteresis | VDDX(UVLOhys) | 0.07 | 0.1 | V | 16 | ||
| Thermal resistance junction-to-ambient | RthJA | 113 | K/W | JEDEC 2s2p (JESD51-7), Pdis = 186 mW; JEDEC board (reference PCB: 89) | 14 | ||
| Thermal resistance junction-to-case (top) | RthJC | 58 | K/W | JEDEC and reference PCB | 14 | ||
| Thermal resistance junction-to-board | RthJB | 35 | K/W | JEDEC board (reference PCB: 44) | 14 | ||
| High-level input current | IIH | 10 | µA | VINX = VDDI; 6.5 V supply | 17 | ||
| Low-level input current | IIL | -10 | µA | VINX = 0 V; 6.5 V supply | 17 | ||
| Input voltage threshold for LH transition (TTL) | VI_LH | 1.4 | 1.9 | V | 6.5 V supply | 17 | |
| Input voltage threshold for HL transition (TTL) | VI_HL | 1 | 1.4 | V | 6.5 V supply | 17 | |
| Low-level output voltage | VOL | 0.4 | V | IOL = -4 mA; 6.5 V supply | 17 | ||
| Low-level output voltage | VOL | 0.4 | V | IOL = -4 mA; 5 V supply | 21 | ||
| Low-level output voltage | VOL | 0.3 | V | IOL = -2 mA; 3.3 V supply | 25 | ||
| Low-level output voltage | VOL | 0.3 | V | IOL = -1 mA; 2.7 V supply | 29 | ||
| Input voltage threshold hysteresis (TTL) | VI_HYS | 0.38 | V | 6.5 V supply | 17 | ||
| Input pull-down resistor | RIN | 825 | kΩ | VINX = VDDI; 6.5 V supply | 17 | ||
| Supply current - DC input | IDD1 | 1.4 | mA | VINx = VDDI; 6.5 V supply | 19 | ||
| Supply current - AC input | IDD1_1Mb | 1.7 | mA | DR = 1 Mbps; 6.5 V supply | 19 | ||
| Supply current - AC input | IDD1_10Mb | 3.5 | mA | DR = 10 Mbps; 6.5 V supply | 19 | ||
| Supply current - AC input | IDD1_20Mb | 5.8 | mA | DR = 20 Mbps; 6.5 V supply | 19 | ||
| Supply current - AC input | IDD2_20Mb | 6 | mA | DR = 20 Mbps; 6.5 V supply | 19 | ||
| Supply current - AC input | IDD1_40Mb | 10 | mA | DR = 40 Mbps; 6.5 V supply | 19 | ||
| Supply current - AC input | IDD2_40Mb | 10.8 | mA | DR = 40 Mbps; 6.5 V supply | 19 | ||
| INx to OUTx turn-on propagation delay | tPDon | 21 | 26 | 33 | ns | From 1.4 V level of rising input to 1.4 V level of corresponding rising output; 6.5 V supply | 20 |
| INx to OUTx turn-off propagation delay | tPDoff | 21 | 26 | 33 | ns | From 1.4 V level of falling input to 1.4 V level of corresponding falling output; 6.5 V supply | 20 |
| Part-to-part propagation delays mismatch | ΔtPD,p-p | 6 | ns | 6.5 V supply | 20 | ||
| Codirectional channel-to-channel propagation delay mismatch | ΔtPD,Ch-Ch | 3 | ns | Within same sample, over operating temperature range, same-direction channels, switching in the same direction; 6.5 V supply | 20 | ||
| Opposite-directional channel-to-channel propagation delay mismatch | ΔtPD,Ch-Ch | 3 | ns | Within same sample, over operating temperature range, opposite-directional channels, switching with the same signal level; 6.5 V supply | 20 | ||
| Pulse width distortion | PWD | 3 | ns | /tPDoff-tPDon/; 6.5 V supply | 20 | ||
| Input pulse width that changes output state | tpw,min | 10 | 11.5 | 16 | ns | Measured with full range of input signal VIN = VDDI; 6.5 V supply | 20 |
| Output signal rise time | trise | 4 | ns | 10% to 90% rising output, CLOAD = 15 pF; 6.5 V supply | 20 | ||
| Output signal fall time | tfall | 4 | ns | 90% to 10% falling output, CLOAD = 15 pF; 6.5 V supply | 20 | ||
| Default output delay time from input power loss | tDO | 0.4 | 2.6 | µs | Measured from VDDX(UVLOoff) = 2.55 V. Power supply ramp rate = 1 V/µs; 6.5 V supply | 20 | |
| Time from UVLO to valid output data | tPU | 3 | µs | Power supply ramp rate = 1 V/µs, DR > 6.6 Mbps; 6.5 V supply | 20 |
CAD (KiCad official)
- Symbol:
2DIB1411FXUMA1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
2dib1411fxuma1-etched.step/2dib1411fxuma1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);2dib1411fxuma1.step/2dib1411fxuma1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (44 pp, sha256
5071620a1e13d9b9, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).