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Contents

README

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TLC3578IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-24

TLC3578IPWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock input from the host processor to clock in the input from SDI and clock out the output via SDO, maximum frequency 25 MHz.
2 FS input Frame sync input from DSP; rising edge indicates the start of a serial data frame being transferred.
3 SDI input Serial data input; first 4 MSBs decoded as one 4-bit command, remaining bits filled with zeros except for WRITE CFR command.
4 EOC/INT output End of conversion (EOC) or interrupt to host processor (INT); EOC used in conversion mode 00 only, goes low at end of sampling.
5 SDO tri_state 3-state serial output for the A/D conversion result, MSB first, in high-impedance state when CS is high.
6 DGND power_in Digital ground return for the internal circuitry.
7 DVDD power_in Digital supply voltage, recommended range 2.7 V to 5.5 V.
8 CS input Chip select; falling edge resets internal 4-bit counter and enables SDI and SCLK, when high SDO is in high-impedance state.
9 A0 input Analog signal input channel 0, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
10 A1 input Analog signal input channel 1, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
11 A2 input Analog signal input channel 2, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
12 A3 input Analog signal input channel 3, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
13 A4 input Analog signal input channel 4, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
14 A5 input Analog signal input channel 5, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
15 A6 input Analog signal input channel 6, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
16 A7 input Analog signal input channel 7, internally multiplexed with driving source impedance ≤ 25 Ω for normal sampling.
17 AVDD power_in Analog supply voltage, recommended range 4.75 V to 5.5 V.
18 AGND power_in Analog ground return for the internal circuitry.
19 REFP input External positive reference input, range 3.96 V to 4.04 V; install decoupling capacitors 10 µF in parallel with 0.1 µF between REFP and REFM.
20 REFM input External low reference input; connect to AGND to establish the ±10 V bipolar input range.
21 COMP passive Internal compensation pin; install 0.1 µF compensation capacitor between this pin and AGND.
22 AGND power_in Analog ground return for the internal circuitry.
23 AVDD power_in Analog supply voltage, recommended range 4.75 V to 5.5 V.
24 CSTART input External sampling trigger signal; high-to-low transition starts sampling, low-to-high transition puts S/H in hold mode and starts conversion with 15 ns internal delay.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Data Acquisition
Pins 24

CAD (KiCad official)

  • Symbol: TLC3578IPWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: tlc3578ipwr-etched.step / tlc3578ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tlc3578ipwr.step / tlc3578ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 a98de3fa366cd8b4, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF