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DSLVDS1048PWT

Public Made by Adom

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Texas Instruments LVDS ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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DSLVDS1048PWT

Texas Instruments · LVDS ICs · TSSOP-16

DSLVDS1048PWT from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RIN1- input Inverting LVDS differential receiver input for channel 1; recommended input voltage range GND to 3 V, differential input low threshold −100 mV, absolute maximum −0.3 V to 3.6 V.
2 RIN1+ input Noninverting LVDS differential receiver input for channel 1; accepts ≥350 mV typical differential signals over common-mode range 0.1 V to 2.3 V (VID = 200 mV pp), differential input high threshold 100 mV.
3 RIN2+ input Noninverting LVDS differential receiver input for channel 2; accepts ≥350 mV typical differential signals over common-mode range 0.1 V to 2.3 V (VID = 200 mV pp), differential input high threshold 100 mV.
4 RIN2- input Inverting LVDS differential receiver input for channel 2; recommended input voltage range GND to 3 V, differential input low threshold −100 mV, absolute maximum −0.3 V to 3.6 V.
5 RIN3- input Inverting LVDS differential receiver input for channel 3; recommended input voltage range GND to 3 V, differential input low threshold −100 mV, absolute maximum −0.3 V to 3.6 V.
6 RIN3+ input Noninverting LVDS differential receiver input for channel 3; accepts ≥350 mV typical differential signals over common-mode range 0.1 V to 2.3 V (VID = 200 mV pp), differential input high threshold 100 mV.
7 RIN4+ input Noninverting LVDS differential receiver input for channel 4; accepts ≥350 mV typical differential signals over common-mode range 0.1 V to 2.3 V (VID = 200 mV pp), differential input high threshold 100 mV.
8 RIN4- input Inverting LVDS differential receiver input for channel 4; recommended input voltage range GND to 3 V, differential input low threshold −100 mV, absolute maximum −0.3 V to 3.6 V.
9 EN* input Active-low receiver enable shared by all four channels; when high the outputs are disabled (TRI-STATE); when low or open with EN high, all receivers are enabled; VIH min 2 V, VIL max 0.8 V.
10 ROUT4 tri_state TRI-STATE CMOS receiver output for channel 4; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output short-circuit current −15 to −100 mA; TRI-STATE leakage ±1 µA typical.
11 ROUT3 tri_state TRI-STATE CMOS receiver output for channel 3; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output short-circuit current −15 to −100 mA; TRI-STATE leakage ±1 µA typical.
12 GND power_in Ground reference pin; all voltages referenced to this node.
13 VCC power_in Power supply pin; recommended +3.3 V ± 0.3 V (3.0 V to 3.6 V), absolute maximum 4 V; bypass with 0.1 µF and 0.001 µF ceramic capacitors in parallel at pin.
14 ROUT2 tri_state TRI-STATE CMOS receiver output for channel 2; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output short-circuit current −15 to −100 mA; TRI-STATE leakage ±1 µA typical.
15 ROUT1 tri_state TRI-STATE CMOS receiver output for channel 1; VOH min 2.7 V at IOH = −0.4 mA, VOL max 0.25 V at IOL = 2 mA; output short-circuit current −15 to −100 mA; TRI-STATE leakage ±1 µA typical.
16 EN input Active-high receiver enable shared by all four channels; when low the outputs are disabled (TRI-STATE); when high with EN* low or open, all receivers are enabled; VIH min 2 V, VIL max 0.8 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: DSLVDS1048PWT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: dslvds1048pwt-etched.step / dslvds1048pwt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dslvds1048pwt.step / dslvds1048pwt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 fe268772875d83aa, retrieved 2026-09-27, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF