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3D Model

Contents

Pinout
Key specifications
Ordering variants
CAD (KiCad official)
Provenance

README

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KSZ8081RNAIA-TR

Microchip · Ethernet Controllers · QFN-24-EP(4x4)

KSZ8081RNAIA-TR from Microchip, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD_1.2	power_in	1.2 V core supply rail (sourced from the on-chip regulator). Decouple with 2.2 µF and 0.1 µF capacitors to ground.
2	VDDA_3.3	power_in	3.3 V analog supply rail for the PHY analog front-end.
3	RXM	bidirectional	Physical receive/transmit signal, negative differential line of the RX/TX pair to the magnetics (Auto MDI/MDI-X swaps RX/TX function).
4	RXP	bidirectional	Physical receive/transmit signal, positive differential line of the RX/TX pair to the magnetics (Auto MDI/MDI-X swaps RX/TX function).
5	TXM	bidirectional	Physical transmit/receive signal, negative differential line of the TX/RX pair to the magnetics (Auto MDI/MDI-X swaps TX/RX function).
6	TXP	bidirectional	Physical transmit/receive signal, positive differential line of the TX/RX pair to the magnetics (Auto MDI/MDI-X swaps TX/RX function).
7	XO	output	Crystal feedback output for the 25 MHz crystal reference. Leave as a no-connect when an external oscillator or clock source is used on XI.
8	XI	input	Reference clock input. In RMII 25 MHz mode accepts a 25 MHz ±50 ppm crystal, oscillator, or external clock. In RMII 50 MHz mode accepts a 50 MHz ±50 ppm oscillator/external clock. RNA power-up default is 25 MHz crystal on this pin.
9	REXT	passive	Sets PHY transmit output current bias. Connect an external 6.49 kΩ 1% resistor from this pin to ground.
10	MDIO	bidirectional	MII management interface data I/O. Open-drain with a weak internal pull-up; requires an external 1.0 kΩ pull-up resistor to VDDIO.
11	MDC	input	MII management interface clock input, synchronous with MDIO data. Has an internal pull-up.
12	RXD1	output	RMII receive data bit 1 output to the MAC. Synchronous with the 50 MHz RMII reference clock; two bits per clock while CRS_DV is asserted. Internally pulled down during power-up/reset (strap-in), output otherwise.
13	RXD0	output	RMII receive data bit 0 output to the MAC. Synchronous with the 50 MHz RMII reference clock; two bits per clock while CRS_DV is asserted. Internally pulled up during power-up/reset (strap-in), output otherwise.
14	VDDIO	power_in	Digital I/O supply rail. Selectable 3.3 V, 2.5 V, or 1.8 V to match the MAC logic level.
15	CRS_DV/PHYAD[1:0]	bidirectional	RMII Carrier Sense / Receive Data Valid output during normal operation. Latched at de-assertion of RST# as PHYAD[1:0]: pull-up → PHY address 0x03, pull-down (default) → PHY address 0x00. PHYAD[4:2] are fixed to 000.
16	REF_CLK	bidirectional	RMII 25 MHz mode: outputs the 50 MHz RMII reference clock to the MAC. RMII 50 MHz mode: no-connect (clock comes in on XI instead). RNA power-up default is 25 MHz mode (this pin drives 50 MHz out).
17	RXER	bidirectional	RMII receive-error output to the MAC. Must latch a pull-down value at the de-assertion of reset for normal operation; add an external pull-down if the MAC drives this line high at reset (or configure Register 16h Bit [15]).
18	INTRP	output	Programmable interrupt output to the MAC/host. Open-drain with a weak internal pull-up; requires an external 1.0 kΩ pull-up resistor to VDDIO.
19	TXEN	input	RMII transmit-enable input from the MAC. Asserted by the MAC while TXD[1:0] carry valid data (two bits per 50 MHz RMII reference clock period).
20	TXD0	input	RMII transmit data bit 0 input from the MAC. Sampled on the 50 MHz RMII reference clock while TXEN is asserted.
21	TXD1	bidirectional	RMII transmit data bit 1 input from the MAC during normal operation. In NAND Tree mode this pin is used as the NAND Tree output for parametric fault-detection testing.
22	GND	power_in	Device ground return.
23	LED0/ANEN_SPEED	bidirectional	Programmable LED0 output during normal operation (modes selected via Register 1Fh bits [5:4]). Latched at reset de-assertion as ANEN_SPEED strap: pull-up (default) enables auto-negotiation and selects 100 Mbps; pull-down disables auto-negotiation and selects 10 Mbps. Values load into Register 0h bits [12]/[13] and Register 4h.
24	RST#	input	Active-low chip reset input. Internal pull-up; drive low to reset the device.
25	PAD	power_in	Exposed thermal paddle on the bottom of the QFN. Must be soldered to the board ground plane.

Key specifications

Parameter	Value
Manufacturer	Microchip
Package	QFN-24-EP(4x4)
Category	Interface
Pins	25

Ordering variants

KSZ8081RNAIA-TR
KSZ8081RNAIA-TRRNACA
KSZ8081RNAIA-TRRNDIA
KSZ8081RNAIA-TRRNDCA

CAD (KiCad official)

Symbol: KSZ8081RNAIA-TR
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip datasheet (None pp, sha256 6d02bb0e0b96569f, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint