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HC32L196KCTA-LQFP64

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XHSC Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllershc32l196kcta-lqfp64factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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HC32L196KCTA-LQFP64

XHSC · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

HC32L196KCTA-LQFP64 from XHSC, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCAP power_out Internal LDO core-supply output for internal circuits only, requiring an external decoupling capacitor of at least 1 µF.
2 PC13 bidirectional General-purpose I/O PC13, also carrying RTC_1HZ, TIM3_CH1B and LVD0 functions.
3 XTLI/PC14 input Input of the 32.768 kHz low-speed crystal oscillator (XTLI), shared with GPIO PC14; load capacitors are set per the crystal maker's requirements.
4 XTLO/PC15 output Output of the 32.768 kHz low-speed crystal oscillator (XTLO), shared with GPIO PC15; the feedback resistor R0 is integrated on-chip.
5 XTHI/PF00 input Input of the 4-32 MHz high-speed crystal/resonator oscillator (XTHI), shared with GPIO PF00 (also I2C0_SDA, UART1_TXD).
6 XTHO/PF01 output Output of the 4-32 MHz high-speed crystal/resonator oscillator (XTHO), shared with GPIO PF01 (also I2C0_SCL, TIM4_CHB, UART1_RXD).
7 RESETB input Active-low reset input with CMOS Schmitt trigger (VIL max 0.3VCC, VIH min 0.7VCC, 200 mV hysteresis) and a non-removable pull-up of about 80 kΩ.
8 SEG27/PC00 bidirectional LCD segment output SEG27, multiplexed with GPIO PC00 and ADC input AIN10 (also LPTIM_GATE, PCNT_S0, UART1_CTS).
9 SEG26/PC01 bidirectional LCD segment output SEG26, multiplexed with GPIO PC01 and ADC input AIN11 (also LPTIM_TOG, TIM5_CHB, UART1_RTS).
10 SEG25/PC02 bidirectional LCD segment output SEG25, multiplexed with GPIO PC02 and ADC input AIN12 (also SPI1_MISO, LPTIM_TOGN, UART2_RXD).
11 SEG24/PC03 bidirectional LCD segment output SEG24, multiplexed with GPIO PC03 and ADC input AIN13 (also SPI1_MOSI, LPTIM_ETR, UART2_TXD).
12 AVSS power_in Analog ground for the ADC, DAC, comparators and other analog blocks; all ground pins must be connected to the external supply system.
13 AVCC power_in Analog supply for the ADC, DAC, OPA and comparators, which must be at the same voltage as DVCC (1.8-5.5 V).
14 SEG23/PA00 bidirectional LCD segment output SEG23, multiplexed with GPIO PA00 and ADC input AIN0 (also UART1_CTS, LPUART1_TXD, TIM0_ETR).
15 SEG22/PA01 bidirectional LCD segment output SEG22, multiplexed with GPIO PA01 and ADC input AIN1 (also UART1_RTS, LPUART1_RXD, SPI1_MOSI).
16 SEG21/PA02 bidirectional LCD segment output SEG21, multiplexed with GPIO PA02 and ADC input AIN2 (also UART1_TXD, VC1_OUT, SPI1_MISO).
17 SEG20/PA03 bidirectional LCD segment output SEG20, multiplexed with GPIO PA03 and ADC input AIN3 (also UART1_RXD, TIM0_GATE, SPI1_CS).
18 PF04 bidirectional General-purpose I/O PF04; no alternate function is listed for this package.
19 PF05 bidirectional General-purpose I/O PF05; no alternate function is listed for this package.
20 SEG19/PA04 bidirectional LCD segment output SEG19, multiplexed with GPIO PA04, ADC input AIN4, DAC_OUT and OPA_OUT0 (also SPI0_CS, UART1_TXD).
21 SEG18/PA05 bidirectional LCD segment output SEG18, multiplexed with GPIO PA05 (also SPI0_SCK, TIM0_ETR, PCA_ECI, XTL_OUT, XTH_OUT).
22 SEG17/PA06 bidirectional LCD segment output SEG17, multiplexed with GPIO PA06 (also SPI0_MISO, PCA_CH0, LPUART0_CTS).
23 SEG16/PA07 bidirectional LCD segment output SEG16, multiplexed with GPIO PA07 (also SPI0_MOSI, PCA_CH1, VC1_OUT).
24 SEG15/PC04 bidirectional LCD segment output SEG15, multiplexed with GPIO PC04 (also LPUART0_TXD, TIM2_ETR, IR_OUT, VC2_OUT).
25 SEG14/PC05 bidirectional LCD segment output SEG14, multiplexed with GPIO PC05 (also LPUART0_RXD, TIM6_CHB, PCA_CH4).
26 SEG13/PB00 bidirectional LCD segment output SEG13, multiplexed with GPIO PB00 (also PCA_CH2, TIM3_CH1B, LPUART0_TXD, RCH_OUT).
27 SEG12/PB01 bidirectional LCD segment output SEG12, multiplexed with GPIO PB01 (also PCA_CH3, PCLK_OUT, TIM3_CH2B, VC2_OUT).
28 SEG11/PB02 bidirectional LCD segment output SEG11, multiplexed with GPIO PB02 (also LPTIM_TOG, PCA_ECI, LPUART1_TXD, TIM4_CHA).
29 SEG10/PB10 bidirectional LCD segment output SEG10, multiplexed with GPIO PB10 (also I2C1_SCL, SPI1_SCK, TIM1_CHA, LPUART0_TXD).
30 SEG9/PB11 bidirectional LCD segment output SEG9, multiplexed with GPIO PB11 (also I2C1_SDA, TIM1_CHB, LPUART0_RXD).
31 DVSS power_in Digital ground; all ground pins must be connected to the external supply system.
32 DVCC power_in Digital supply for 1.8-5.5 V operation, to be decoupled by a capacitor placed close to the pin.
33 PB12/SEG8 bidirectional LCD segment output SEG8, multiplexed with GPIO PB12 (also SPI1_CS, TIM3_BK, LPUART0_TXD, TIM0_BK).
34 PB13/SEG7 bidirectional LCD segment output SEG7, multiplexed with GPIO PB13 (also SPI1_SCK, I2C1_SCL, TIM3_CH0B, LPUART0_CTS).
35 PB14/SEG6 bidirectional LCD segment output SEG6, multiplexed with GPIO PB14 (also SPI1_MISO, I2C1_SDA, TIM3_CH1B, RTC_1HZ).
36 PB15/SEG5 bidirectional LCD segment output SEG5, multiplexed with GPIO PB15 (also SPI1_MOSI, TIM3_CH2B, TIM0_CHB, LPUART1_RXD).
37 PC06/SEG4 bidirectional LCD segment output SEG4, multiplexed with GPIO PC06 (also PCA_CH0, TIM4_CHA, TIM2_CHA, UART3_RXD).
38 PC07/SEG3 bidirectional LCD segment output SEG3, multiplexed with GPIO PC07 (also PCA_CH1, TIM5_CHA, TIM2_CHB, UART3_TXD).
39 PC08/SEG2 bidirectional LCD segment output SEG2, multiplexed with GPIO PC08 (also PCA_CH2, TIM6_CHA, TIM2_ETR, UART3_CTS).
40 PC09/SEG1 bidirectional LCD segment output SEG1, multiplexed with GPIO PC09 (also PCA_CH3, TIM4_CHB, TIM1_ETR, UART3_RTS).
41 PA08/SEG0 bidirectional LCD segment output SEG0, multiplexed with GPIO PA08 (also UART0_TXD, TIM3_CH0A, TIM1_GATE, TIM4_CHA).
42 PA09/COM0 bidirectional LCD common output COM0, multiplexed with GPIO PA09 (also UART0_TXD, TIM3_CH1A, I2C0_SCL, HCLK_OUT).
43 PA10/COM1 bidirectional LCD common output COM1, multiplexed with GPIO PA10 (also UART0_RXD, TIM3_CH2A, I2C0_SDA, PCLK_OUT).
44 PA11/COM2 bidirectional LCD common output COM2, multiplexed with GPIO PA11 (also UART0_CTS, I2C1_SCL, VC0_OUT, SPI0_MISO).
45 PA12/COM3 bidirectional LCD common output COM3, multiplexed with GPIO PA12 (also UART0_RTS, I2C1_SDA, VC1_OUT, SPI0_MOSI).
46 PA13/SWDIO bidirectional Serial-wire debug data I/O (SWDIO), multiplexed with GPIO PA13 (also IR_OUT, UART0_RXD, LVD_OUT, VC2_OUT).
47 PF06 bidirectional General-purpose I/O PF06 (also I2C1_SCL, LPUART1_CTS, UART0_CTS).
48 PF07 bidirectional General-purpose I/O PF07 (also I2C1_SDA, LPUART1_RTS, UART0_RTS).
49 PA14/SWCLK input Serial-wire debug clock input (SWCLK), multiplexed with GPIO PA14 (also UART1_TXD, UART0_TXD, TIM3_CH2A, LVD_OUT).
50 PA15 bidirectional General-purpose I/O PA15 (also SPI0_CS, UART1_RXD, LPUART1_RTS, TIM0_ETR, TIM0_CHA).
51 PC10/COM4/SEG39 bidirectional LCD common output COM4 / segment output SEG39, multiplexed with GPIO PC10 (also LPUART1_TXD, LPUART0_TXD, PCA_CH2).
52 PC11/COM5/SEG38 bidirectional LCD common output COM5 / segment output SEG38, multiplexed with GPIO PC11 (also LPUART1_RXD, LPUART0_RXD, PCA_CH3, PCNT_S0FO).
53 PC12/COM6/SEG37 bidirectional LCD common output COM6 / segment output SEG37, multiplexed with GPIO PC12 (also LPUART0_TXD, LPUART1_TXD, PCA_CH4, PCNT_S1FO).
54 PD02/COM7/SEG36 bidirectional LCD common output COM7 / segment output SEG36, multiplexed with GPIO PD02 (also PCA_ECI, LPUART0_RTS, TIM1_ETR).
55 PB03/SEG35/VLCDH bidirectional LCD segment output SEG35 and VLCDH pin used in external resistor and external capacitor LCD modes, multiplexed with GPIO PB03 (also SPI0_SCK, TIM0_CHB, TIM1_GATE, XTL_OUT).
56 PB04/SEG34/VLCD3 bidirectional LCD segment output SEG34 and VLCD3 pin used in external resistor and external capacitor LCD modes, multiplexed with GPIO PB04 (also SPI0_MISO, PCA_CH0, TIM2_BK, UART0_CTS).
57 PB05/SEG33/VLCD2 bidirectional LCD segment output SEG33 and VLCD2 pin used in external resistor and external capacitor LCD modes, multiplexed with GPIO PB05 (also SPI0_MOSI, TIM1_BK, PCA_CH1, UART0_RTS).
58 PB06/SEG32/VLCD1 bidirectional LCD segment output SEG32 and VLCD1 pin used in external resistor and external capacitor LCD modes, multiplexed with GPIO PB06 (also I2C0_SCL, UART0_TXD, TIM1_CHB, LPTIM_ETR).
59 PB07/SEG31 bidirectional LCD segment output SEG31, multiplexed with GPIO PB07 (also I2C0_SDA, UART0_RXD, TIM2_CHB, LPUART1_CTS).
60 BOOT0 input Boot mode select sampled at reset: high selects ISP programming mode, low selects user mode with Flash programming via SWD.
61 PB08/SEG29 bidirectional LCD segment output SEG29, multiplexed with GPIO PB08 (also I2C0_SCL, TIM1_CHA, TIM2_CHA, TIM0_GATE, UART0_TXD).
62 PB09/SEG28 bidirectional LCD segment output SEG28, multiplexed with GPIO PB09 (also I2C0_SDA, IR_OUT, SPI1_CS, TIM2_CHA, UART0_RXD).
63 DVSS power_in Digital ground; all ground pins must be connected to the external supply system.
64 DVCC power_in Digital supply for 1.8-5.5 V operation, to be decoupled by a capacitor placed close to the pin.

Key specifications

Parameter Value
Manufacturer XHSC
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External main supply voltage VCC-VSS (incl. AVCC and DVCC) VCC - VSS -0.3 5.5 V 外部主供电电压(包含AVCC和DVCC) 49
Voltage difference between supply pins /ΔVCCx/ 50 mV 不同供电引脚之间的电压差 49
Voltage difference between ground pins /VSSx - VSS/ 50 mV 不同接地引脚之间的电压差 49
Total current through DVCC/AVCC supply lines IVCC 300 mA 经过DVCC/AVCC电源线的总电流(供应电流) 49
Total current through VSS ground lines IVSS 300 mA 经过VSS地线的总电流(流出电流) 49
Output sink current on any I/O and control pin IIO 25 mA 任意I/O和控制引脚上的输出灌电流 49
Output source current on any I/O and control pin IIO -25 mA 任意I/O和控制引脚上的输出电流 49
Injection current on RESETB pin IINJ(PIN) -5 5 mA RESETB引脚的注入电流 +/-5 mA 49
Injection current on XTHI and XTLI pins IINJ(PIN) -5 5 mA XTH的XTHI引脚和XTL的XTLI引脚的注入电流 49
Injection current on other pins IINJ(PIN) -5 5 mA 其他引脚的注入电流 49
Sum of injection current on all I/O and control pins ∑IINJ(PIN) -25 25 mA 所有I/O和控制引脚上的总注入电流 49
External input voltage range Vex 0 V 53
LVD detection threshold tolerance Vlevel -3.5 3.5 % all LVD_CR.VTDS settings 53
Internal 2.5V reference voltage VREF25 2.475 2.5 2.525 V 常温25°C 3.3V 54
Internal 2.5V reference voltage VREF25 2.463 2.5 2.525 V -40 85°C 2.85.5V 54
Internal 1.5V reference voltage VREF15 1.485 1.5 1.515 V 常温25°C 3.3V 54
Internal 1.5V reference voltage VREF15 1.477 1.5 1.519 V -40 85°C 1.85.5V 54
IDD Run while(1) in Flash, RCH 4M IDD 1000 1430 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 8M IDD 1890 2710 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 16M IDD 3710 5160 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 22.12M IDD 5010 7000 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 24M IDD 5400 7570 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 16M IDD 3930 4990 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 24M IDD 5480 7080 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 32M IDD 6590 7640 μA All peripherals clock ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 40M IDD 8100 9470 μA All peripherals clock ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 48M IDD 9610 11200 μA All peripherals clock ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH8M to 16M IDD 3990 5030 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH8M to 24M IDD 5530 7130 μA All peripherals clock ON, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH8M to 32M IDD 6640 7680 μA All peripherals clock ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH8M to 40M IDD 8160 9470 μA All peripherals clock ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH8M to 48M IDD 9670 11240 μA All peripherals clock ON, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 4M (peripherals OFF) IDD 610 990 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 8M (peripherals OFF) IDD 1090 1830 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 16M (peripherals OFF) IDD 2080 3350 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 22.12M (peripherals OFF) IDD 2770 4480 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, RCH 24M (peripherals OFF) IDD 2970 4810 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 16M (peripherals OFF) IDD 2290 3150 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 24M (peripherals OFF) IDD 3060 4360 μA All peripherals clock OFF, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 32M (peripherals OFF) IDD 3410 4020 μA All peripherals clock OFF, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
IDD Run while(1) in Flash, PLL from RCH4M to 40M (peripherals OFF) IDD 4110 4950 μA All peripherals clock OFF, FlashWait=1, VCAP=1.5V, VCC=1.8-5.5V, TA=-40~85°C 55
Operating supply voltage 1.8 5.5 V 工作条件 1
Operating temperature -40 85 ℃ 工作条件 1
LVD detection threshold (LVD_CR.VTDS=0000) Vlevel 1.8 V LVD_CR.VTDS=0000 53
LVD detection threshold (LVD_CR.VTDS=0001) Vlevel 1.9 V LVD_CR.VTDS=0001 53
LVD detection threshold (LVD_CR.VTDS=0010) Vlevel 2 V LVD_CR.VTDS=0010 53
LVD detection threshold (LVD_CR.VTDS=0011) Vlevel 2.1 V LVD_CR.VTDS=0011 53
LVD detection threshold (LVD_CR.VTDS=0100) Vlevel 2.2 V LVD_CR.VTDS=0100 53
LVD detection threshold (LVD_CR.VTDS=0101) Vlevel 2.3 V LVD_CR.VTDS=0101 53
LVD detection threshold (LVD_CR.VTDS=0110) Vlevel 2.4 V LVD_CR.VTDS=0110 53
LVD detection threshold (LVD_CR.VTDS=0111) Vlevel 2.5 V LVD_CR.VTDS=0111 53
LVD detection threshold (LVD_CR.VTDS=1000) Vlevel 2.6 V LVD_CR.VTDS=1000 53
LVD detection threshold (LVD_CR.VTDS=1001) Vlevel 2.7 V LVD_CR.VTDS=1001 53
LVD detection threshold (LVD_CR.VTDS=1010) Vlevel 2.8 V LVD_CR.VTDS=1010 53
LVD detection threshold (LVD_CR.VTDS=1011) Vlevel 2.9 V LVD_CR.VTDS=1011 53
LVD detection threshold (LVD_CR.VTDS=1100) Vlevel 3 V LVD_CR.VTDS=1100 53
LVD detection threshold (LVD_CR.VTDS=1101) Vlevel 3.1 V LVD_CR.VTDS=1101 53
LVD detection threshold (LVD_CR.VTDS=1110) Vlevel 3.2 V LVD_CR.VTDS=1110 53
LVD detection threshold (LVD_CR.VTDS=1111) Vlevel 3.3 V LVD_CR.VTDS=1111 53

CAD (KiCad official)

  • Symbol: HC32L196KCTA-LQFP64
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: hc32l196kcta-lqfp64-etched.step / hc32l196kcta-lqfp64-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hc32l196kcta-lqfp64.step / hc32l196kcta-lqfp64.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XHSC datasheet (98 pp, sha256 3664a76916c1dfdf, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF