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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83TG720SWRHARQ1

Texas Instruments · Ethernet Transceivers · QFN-36-EP(6x6)

DP83TG720SWRHARQ1 from Texas Instruments, in a QFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MDC	input	Management data clock that synchronizes MDIO transfers; it may be stopped by the external management entity when the bus is idle, and the datasheet gives an MDC frequency of 2.5 to 20 MHz at 25 pF load.
2	INT_N	output	Active-low interrupt output with weak internal pull-up (open-drain); it stays low until the interrupt flag is cleared by register access, and can be made active-high through register 0x0011.
3	RESET_N	input	Active-low reset input with internal pull-up that must be held low for at least 10 µs to force reset; strap pins are re-sampled when it is released.
4	XO	output	Reference clock output used only with a crystal across XI and XO; it is left unconnected when a CMOS-level oscillator drives XI.
5	XI	input	Reference clock input for a 25 MHz ±100 ppm crystal or CMOS-level oscillator, with VIH of 1.3 V minimum and VIL of 0.5 V maximum.
6	LED_1 / GPIO_1	bidirectional	LED_1 indicates link status and blinks on TX/RX activity; it is a strap pin with internal pull-down of 9 kΩ (typical) and can be reconfigured as GPIO_1.
7	VSLEEP	power_in	Sleep-domain supply of 3.3 V (2.97 V to 3.63 V); connect it to VDDA3P3 if sleep mode is not used.
8	WAKE	input	Active-high local wake input in the VSLEEP domain that wakes the PHY from sleep, with internal pull-down of 50 kΩ (typical); it may be tied directly to VSLEEP if sleep is unused.
9	VDD1P0	power_in	1.0 V core supply (0.95 V to 1.1 V); see the datasheet decoupling recommendations.
10	INH	output	Active-high PMOS open-drain output that is released in sleep so an external 10 kΩ pull-down can pull the line to ground, and otherwise drives high to the VSLEEP rail.
11	VDDA3P3	power_in	3.3 V core analog supply (2.97 V to 3.63 V); see the datasheet decoupling recommendations.
12	TRD_P	bidirectional	Positive leg of the 1000BASE-T1 differential MDI pair, which is rated -0.5 V to 4 V and must be ESD-protected and coupled through the common-mode network per the layout guidance.
13	TRD_M	bidirectional	Negative leg of the 1000BASE-T1 differential MDI pair, which is rated -0.5 V to 4 V and must be ESD-protected and coupled through the common-mode network per the layout guidance.
14	STRP_1	input	Strap 1 pin sampled at power-up and reset to set the PHY_AD address bits, with internal pull-down of 6.3 kΩ (typical).
15	RX_CTRL	output	RGMII receive control that combines RX_DV and RX_ER, with RX_DV on the rising edge and RX_ER on the falling edge of RX_CLK; in SGMII mode it is used only as a strap.
16	CLKOUT / GPIO_2	bidirectional	Outputs a buffered copy of the 25 MHz XI reference by default, and can be disabled by writing 0x0453 = 0x0006 if not used.
17	DNC	unconnected	Do not connect; test structures on this pin must be left floating to avoid damage or entering an incorrect PHY mode.
18	DNC	unconnected	Do not connect; test structures on this pin must be left floating to avoid damage or entering an incorrect PHY mode.
19	DNC	unconnected	Do not connect; test structures on this pin must be left floating to avoid damage or entering an incorrect PHY mode.
20	DNC	unconnected	Do not connect; test structures on this pin must be left floating to avoid damage or entering an incorrect PHY mode.
21	VDD1P0	power_in	1.0 V core supply (0.95 V to 1.1 V); see the datasheet decoupling recommendations.
22	VDDIO	power_in	I/O supply that operates at 1.8 V, 2.5 V or 3.3 V (1.62 V to 3.63 V across the three operating points); see the datasheet decoupling recommendations.
23	RX_D3 / RX_M	output	In RGMII mode it outputs decoded receive data bit 3 synchronous to the RX_CLK rising edge, and in SGMII mode it is the negative leg of the differential data output to the MAC; it is a strap pin with internal pull-down of 9 kΩ.
24	RX_D2 / RX_P	output	In RGMII mode it outputs decoded receive data bit 2 synchronous to the RX_CLK rising edge, and in SGMII mode it is the positive leg of the differential data output to the MAC; it is a strap pin with internal pull-down of 9 kΩ.
25	RX_D1	output	In RGMII mode it outputs decoded receive data bit 1 synchronous to the RX_CLK rising edge; it is a strap pin with internal pull-down of 9 kΩ.
26	RX_D0	output	In RGMII mode it outputs decoded receive data bit 0 synchronous to the RX_CLK rising edge; it is a strap pin with internal pull-down of 9 kΩ.
27	RX_CLK	output	In RGMII mode the PHY supplies this 125 MHz receive clock to the MAC; it is not used in SGMII mode.
28	TX_CLK	input	In RGMII mode the MAC supplies this 125 MHz transmit clock to the PHY; it is not used in SGMII mode.
29	TX_CTRL	input	RGMII transmit control that combines TX_EN and TX_ER, with TX_EN sampled before the rising edge of TX_CLK and TX_ER on its falling edge; it is not used in SGMII mode.
30	TX_D3	input	RGMII transmit data bit 3 from the MAC, sampled on TX_CLK.
31	TX_D2	input	RGMII transmit data bit 2 from the MAC, sampled on TX_CLK.
32	TX_D1 / TX_P	input	In RGMII mode it is transmit data bit 1 from the MAC, and in SGMII mode it is the positive leg of the differential data input from the MAC.
33	TX_D0 / TX_M	input	In RGMII mode it is transmit data bit 0 from the MAC, and in SGMII mode it is the negative leg of the differential data input from the MAC.
34	VDDIO	power_in	Second I/O supply pin for the VDDIO domain (1.8 V, 2.5 V or 3.3 V); see the datasheet decoupling recommendations.
35	LED_0 / GPIO_0	bidirectional	LED_0 indicates link status and also acts as the MDI master/slave strap (internal pull-down, so slave by default), and it can be reconfigured as GPIO_0.
36	MDIO	bidirectional	Open-drain management data input/output that requires an external 2.2 kΩ pull-up to VDDIO and is latched on the rising edge of MDC.
37	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-36-EP(6x6)
Category	Interface
Pins	37

CAD (KiCad official)

Symbol: DP83TG720SWRHARQ1
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: QFN-36-EP(6x6) (KiCad packages3D, STEP)
3D model files: dp83tg720swrharq1-etched.step / dp83tg720swrharq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83tg720swrharq1.step / dp83tg720swrharq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (178 pp, sha256 646e55196d701cdd, retrieved 2026-10-12, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF