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TMS5700332BPZQQ1

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

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TMS5700332BPZQQ1

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

TMS5700332BPZQQ1 from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GIOA[0]/SPI3nCS[3] bidirectional General-purpose I/O GIOA[0] (default) with alternate function SPI3nCS[3]; programmable 20 µA pulldown at reset, and GPIO terminals can generate interrupts on rising, falling or both edges.
2 GIOA[1]/SPI3nCS[2] bidirectional General-purpose I/O GIOA[1] (default) with alternate function SPI3nCS[2]; programmable 20 µA pulldown at reset, and can generate edge interrupts to the CPU.
3 FLTP1 input Flash test pin; for proper operation it must connect only to a test pad or be left not connected (NC), and the test pad must not be exposed to ESD in the final product.
4 FLTP2 input Flash test pin; for proper operation it must connect only to a test pad or be left not connected (NC), and the test pad must not be exposed to ESD in the final product.
5 GIOA[2]/SPI3nCS[1] bidirectional General-purpose I/O GIOA[2] (default) with alternate function SPI3nCS[1]; programmable 20 µA pulldown at reset, and can generate edge interrupts to the CPU.
6 VCCIO power_in 3.3-V I/O supply (recommended 3.0 V to 3.6 V).
7 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
8 GIOA[3]/SPI2nCS[3] bidirectional General-purpose I/O GIOA[3] (default) with alternate function SPI2nCS[3]; programmable 20 µA pulldown at reset, and can generate edge interrupts to the CPU.
9 GIOA[4]/SPI2nCS[2] bidirectional General-purpose I/O GIOA[4] (default) with alternate function SPI2nCS[2]; programmable 20 µA pulldown at reset, and can generate edge interrupts to the CPU.
10 GIOA[5]/EXTCLKIN bidirectional General-purpose I/O GIOA[5] or External Clock In (EXTCLKIN); 20 µA pulldown at reset, and can generate edge interrupts to the CPU.
11 N2HET[22] bidirectional N2HET timer input capture or output compare channel 22, or GPIO; each terminal has a programmable suppression filter and 20 µA programmable pulldown at reset.
12 GIOA[6]/SPI2nCS[1]/N2HET[31] bidirectional General-purpose I/O GIOA[6] (default) with alternate functions SPI2nCS[1] and N2HET[31]; programmable 20 µA pulldown at reset.
13 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
14 OSCIN input Input from external crystal/resonator or external clock input for the main oscillator.
15 KELVIN_GND power_in Dedicated ground for the main oscillator.
16 OSCOUT output Output to external crystal/resonator for the main oscillator.
17 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
18 GIOA[7]/N2HET[29] bidirectional General-purpose I/O GIOA[7] (default) with alternate function N2HET[29]; programmable 20 µA pulldown at reset, and can generate edge interrupts to the CPU.
19 N2HET[0] bidirectional N2HET timer input capture or output compare channel 0, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
20 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
21 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
22 N2HET[2] bidirectional N2HET timer input capture or output compare channel 2, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
23 SPI2nCS[0] bidirectional SPI2 chip select 0, or GPIO.
24 TEST bidirectional Test enable; must be connected to ground directly or through a pulldown resistor (fixed 100 µA pulldown).
25 N2HET[4] bidirectional N2HET timer input capture or output compare channel 4, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
26 N2HET[6] bidirectional N2HET timer input capture or output compare channel 6, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
27 MIBSPI1nCS[2]/N2HET[20]/N2HET[19] bidirectional MibSPI1 chip select 2 (default) with alternate functions N2HET[20] and N2HET[19]; programmable 20 µA pulldown at reset.
28 VCCIO power_in 3.3-V I/O supply (recommended 3.0 V to 3.6 V).
29 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
30 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
31 nPORRST input Power-on reset input (cold reset); external supply monitor circuitry must drive it low when any microcontroller supply is out of its specified range; has a glitch filter and 100 µA pulldown.
32 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
33 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
34 SPI3SOMI bidirectional SPI3 Slave-Out-Master-In, or GPIO.
35 SPI3SIMO bidirectional SPI3 Slave-In-Master-Out, or GPIO.
36 SPI3CLK/EQEPA bidirectional SPI3 serial clock, or GPIO; alternate function is eQEP Input A; pullup 20 µA fixed at reset.
37 SPI3nENA/EQEPB bidirectional SPI3 enable, or GPIO; alternate function is eQEP Input B.
38 SPI3nCS[0]/EQEPI bidirectional SPI3 chip select 0, or GPIO; alternate function is eQEP Index.
39 MIBSPI1nCS[3]/N2HET[26] bidirectional MibSPI1 chip select 3, or GPIO; alternate function N2HET[26].
40 ADIN[16] input MibADC analog input channel 16.
41 ADIN[17] input MibADC analog input channel 17.
42 ADIN[0] input MibADC analog input channel 0.
43 ADIN[7] input MibADC analog input channel 7.
44 ADIN[20] input MibADC analog input channel 20.
45 ADIN[21] input MibADC analog input channel 21.
46 VCCAD/ADREFHI power_in MibADC operating supply and ADC high reference level (recommended 3.0 V to 3.6 V).
47 VSSAD/ADREFLO power_in MibADC supply ground and ADC low reference level (recommended -0.1 V to 0.1 V).
48 ADIN[9] input MibADC analog input channel 9.
49 ADIN[1] input MibADC analog input channel 1.
50 ADIN[10] input MibADC analog input channel 10.
51 ADIN[2] input MibADC analog input channel 2.
52 ADIN[3] input MibADC analog input channel 3.
53 ADIN[11] input MibADC analog input channel 11.
54 ADIN[4] input MibADC analog input channel 4.
55 ADIN[5] input MibADC analog input channel 5.
56 ADIN[6] input MibADC analog input channel 6.
57 ADIN[8] input MibADC analog input channel 8.
58 ADEVT/N2HET[28] bidirectional ADC event trigger or GPIO, with alternate function N2HET[28]; programmable 20 µA pullup at reset.
59 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
60 VCCIO power_in 3.3-V I/O supply (recommended 3.0 V to 3.6 V).
61 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
62 CAN1TX bidirectional CAN1 transmit, or GPIO; programmable 20 µA pullup at reset.
63 CAN1RX bidirectional CAN1 receive, or GPIO; programmable 20 µA pullup at reset.
64 N2HET[24] bidirectional N2HET timer input capture or output compare channel 24, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
65 MIBSPI1SIMO bidirectional MibSPI1 Slave-In-Master-Out, or GPIO.
66 MIBSPI1SOMI bidirectional MibSPI1 Slave-Out-Master-In, or GPIO.
67 MIBSPI1CLK bidirectional MibSPI1 serial clock, or GPIO; programmable 20 µA pullup at reset.
68 MIBSPI1nENA/N2HET[23]/N2HET[30] bidirectional MibSPI1 enable, or GPIO; alternate functions N2HET[23] and N2HET[30].
69 SPI2SOMI bidirectional SPI2 Slave-Out-Master-In, or GPIO; drive strength selectable as 8 mA (default, SRS=0) or 2 mA (SRS=1).
70 SPI2SIMO bidirectional SPI2 Slave-In-Master-Out, or GPIO; drive strength selectable as 8 mA (default, SRS=0) or 2 mA (SRS=1).
71 SPI2CLK bidirectional SPI2 serial clock, or GPIO; drive strength selectable as 8 mA (default, SRS=0) or 2 mA (SRS=1).
72 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
73 MIBSPI1nCS[0] bidirectional MibSPI1 chip select 0, or GPIO.
74 N2HET[8] bidirectional N2HET timer input capture or output compare channel 8, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
75 TMS bidirectional JTAG test select input (fixed 100 µA pullup).
76 nTRST bidirectional JTAG test hardware reset (fixed 100 µA pulldown).
77 TDI bidirectional JTAG test data in (fixed 100 µA pullup).
78 TDO output JTAG test data out (fixed 100 µA pulldown when not driven).
79 TCK input JTAG test clock (fixed 100 µA pulldown).
80 RTCK output JTAG return test clock output.
81 nRST bidirectional System reset; external circuitry can assert a system reset by driving it low, external pullup recommended, 100 µA pullup, with glitch filter.
82 nERROR bidirectional ESM error signal; driven low to indicate an error of high severity, 20 µA pulldown.
83 N2HET[10] bidirectional N2HET timer input capture or output compare channel 10, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
84 ECLK bidirectional External prescaled clock output (frequency is a programmable ratio of VCLK), or GPIO; programmable 20 µA pulldown at reset.
85 VCCIO power_in 3.3-V I/O supply (recommended 3.0 V to 3.6 V).
86 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
87 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.
88 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
89 N2HET[12] bidirectional N2HET timer input capture or output compare channel 12, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
90 N2HET[14] bidirectional N2HET timer input capture or output compare channel 14, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
91 CAN2TX bidirectional CAN2 transmit, or GPIO; programmable 20 µA pullup at reset.
92 CAN2RX bidirectional CAN2 receive, or GPIO; programmable 20 µA pullup at reset.
93 MIBSPI1nCS[1]/EQEPS/N2HET[17] bidirectional MibSPI1 chip select 1 (default) with alternate functions eQEP Strobe (EQEPS) and N2HET[17]; programmable 20 µA pullup at reset.
94 LINRX bidirectional LIN receive, or GPIO; programmable 20 µA pullup at reset.
95 LINTX bidirectional LIN transmit, or GPIO.
96 VCCP power_in 3.3-V flash external pump supply (recommended 3.0 V to 3.6 V), required for flash read, program and erase.
97 N2HET[16] bidirectional N2HET timer input capture or output compare channel 16, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
98 N2HET[18] bidirectional N2HET timer input capture or output compare channel 18, or GPIO; programmable 20 µA pulldown at reset and programmable suppression filter.
99 VCC power_in 1.2-V digital logic and RAM core supply (recommended 1.14 V to 1.32 V).
100 VSS power_in Device ground reference, a single ground for all supplies except the ADC supply.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: TMS5700332BPZQQ1
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: tms5700332bpzqq1-etched.step / tms5700332bpzqq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tms5700332bpzqq1.step / tms5700332bpzqq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (114 pp, sha256 5d616069ef21fdcb, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF